93 	switch (b->address) {  in bank4_names()
105 		WARN(1, "Funny MSR: 0x%08x\n", b->address);  in bank4_names()
133 		       b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
140 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
156 	rdmsr(tr->b->address, lo, hi);  in threshold_restart_bank()
193 	wrmsr(tr->b->address, lo, hi);  in threshold_restart_bank()
255 	u32 low = 0, high = 0, address = 0;  in mce_amd_feature_init()  local
262 				address = MSR_IA32_MCx_MISC(bank);  in mce_amd_feature_init()
264 				address = (low & MASK_BLKPTR_LO) >> 21;  in mce_amd_feature_init()
265 				if (!address)  in mce_amd_feature_init()
268 				address += MCG_XBLK_ADDR;  in mce_amd_feature_init()
270 				++address;  in mce_amd_feature_init()
272 			if (rdmsr_safe(address, &low, &high))  in mce_amd_feature_init()
289 			b.address		= address;  in mce_amd_feature_init()
388 	u32 low = 0, high = 0, address = 0;  in amd_threshold_interrupt()  local
398 				address = MSR_IA32_MCx_MISC(bank);  in amd_threshold_interrupt()
400 				address = (low & MASK_BLKPTR_LO) >> 21;  in amd_threshold_interrupt()
401 				if (!address)  in amd_threshold_interrupt()
403 				address += MCG_XBLK_ADDR;  in amd_threshold_interrupt()
405 				++address;  in amd_threshold_interrupt()
408 			if (rdmsr_safe(address, &low, &high))  in amd_threshold_interrupt()
504 	rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);  in show_error_count()
569 				     unsigned int block, u32 address)  in allocate_threshold_blocks()  argument
578 	if (rdmsr_safe_on_cpu(cpu, address, &low, &high))  in allocate_threshold_blocks()
599 	b->address		= address;  in allocate_threshold_blocks()
627 		address = (low & MASK_BLKPTR_LO) >> 21;  in allocate_threshold_blocks()
628 		if (!address)  in allocate_threshold_blocks()
630 		address += MCG_XBLK_ADDR;  in allocate_threshold_blocks()
632 		++address;  in allocate_threshold_blocks()
635 	err = allocate_threshold_blocks(cpu, bank, ++block, address);  in allocate_threshold_blocks()