Lines Matching refs:__u8
61 __u8 last_irr; /* edge detection */
62 __u8 irr; /* interrupt request register */
63 __u8 imr; /* interrupt mask register */
64 __u8 isr; /* interrupt service register */
65 __u8 priority_add; /* highest irq priority */
66 __u8 irq_base;
67 __u8 read_reg_select;
68 __u8 poll;
69 __u8 special_mask;
70 __u8 init_state;
71 __u8 auto_eoi;
72 __u8 rotate_on_auto_eoi;
73 __u8 special_fully_nested_mode;
74 __u8 init4; /* true if 4 byte init */
75 __u8 elcr; /* PIIX edge/trigger selection */
76 __u8 elcr_mask;
89 __u8 vector;
90 __u8 delivery_mode:3;
91 __u8 dest_mode:1;
92 __u8 delivery_status:1;
93 __u8 polarity:1;
94 __u8 remote_irr:1;
95 __u8 trig_mode:1;
96 __u8 mask:1;
97 __u8 reserve:7;
98 __u8 reserved[4];
99 __u8 dest_id;
131 __u8 type;
132 __u8 present, dpl, db, s, l, g, avl;
133 __u8 unusable;
134 __u8 padding;
158 __u8 fpr[8][16];
161 __u8 ftwx; /* in fxsave format */
162 __u8 pad1;
166 __u8 xmm[16][16];
234 __u8 count_latched;
235 __u8 status_latched;
236 __u8 status;
237 __u8 read_state;
238 __u8 write_state;
239 __u8 write_latch;
240 __u8 rw_mode;
241 __u8 mode;
242 __u8 bcd;
243 __u8 gate;
278 __u8 pit_reinject;
279 __u8 reserved[31];
295 __u8 injected;
296 __u8 nr;
297 __u8 has_error_code;
298 __u8 pad;
302 __u8 injected;
303 __u8 nr;
304 __u8 soft;
305 __u8 shadow;
308 __u8 injected;
309 __u8 pending;
310 __u8 masked;
311 __u8 pad;
316 __u8 smm;
317 __u8 pending;
318 __u8 smm_inside_nmi;
319 __u8 latched_init;