Lines Matching refs:r0
63 mov r0, #PRIV_MODE @ ensure priv mode
64 or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs
65 mov.a asr, r0
68 movc r0, p0.c0, #0 @ cpuid
71 and r0, r1, r0
72 cxor.a r0, r2
78 movl r0, #KERNEL_PGD_PADDR @ page table address
80 add r2, r0, #0x1000
81 101: stw.w r1, [r0]+, #4
82 stw.w r1, [r0]+, #4
83 stw.w r1, [r0]+, #4
84 stw.w r1, [r0]+, #4
85 cxor.a r0, r2
108 add r0, r4, #(KERNEL_START & 0xff000000) >> 20
109 stw.w r1, [r0+], #(KERNEL_START & 0x00c00000) >> 20
111 add r0, r0, #4
113 102: csub.a r0, r6
116 stw.w r1, [r0]+, #4
122 add r0, r4, #PAGE_OFFSET >> 20
124 stw r6, [r0]
132 mov r0, #0
133 movc p0.c5, r0, #28 @ cache invalidate all
135 movc p0.c6, r0, #6 @ TLB invalidate all
142 movl r0, #0x201f @ control register setting
150 andn r0, r0, #CR_A
153 andn r0, r0, #CR_D
156 andn r0, r0, #CR_B
159 andn r0, r0, #CR_I
175 mov r0, r0
176 movc p0.c1, r0, #0 @ write control reg
223 andn r1, r0, #CR_A @ Clear 'A' bit
224 stm (r0, r1), [r8]+ @ Save control register values
239 adr r0, str_p1
241 mov r0, r9
243 adr r0, str_p2