179 static void find_regs(tilegx_bundle_bits bundle, uint64_t *rd, uint64_t *ra,  in find_regs()  argument
202 		if (rd) {  in find_regs()
204 			*rd = reg;  in find_regs()
205 			alias_reg_map = (1ULL << *rd) | (1ULL << *ra);  in find_regs()
250 		if (rd)	{  in find_regs()
254 			*rd = reg;  in find_regs()
255 			alias_reg_map = (1ULL << *rd) | (1ULL << *ra);  in find_regs()
316 static bool check_regs(uint64_t rd, uint64_t ra, uint64_t rb,  in check_regs()  argument
326 	if (rd != -1) {  in check_regs()
327 		if ((rd >= 56) && (rd != TREG_ZERO))  in check_regs()
377 static tilegx_bundle_bits  jit_x0_addi(int rd, int ra, int imm8)  in jit_x0_addi()  argument
381 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_addi()
386 static tilegx_bundle_bits  jit_x1_ldna(int rd, int ra)  in jit_x1_ldna()  argument
390 		create_Dest_X1(rd) | create_SrcA_X1(ra);  in jit_x1_ldna()
394 static tilegx_bundle_bits  jit_x0_dblalign(int rd, int ra, int rb)  in jit_x0_dblalign()  argument
398 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_dblalign()
464 static tilegx_bundle_bits  jit_x1_ld(int rd, int ra)  in jit_x1_ld()  argument
468 		create_Dest_X1(rd) | create_SrcA_X1(ra);  in jit_x1_ld()
472 static tilegx_bundle_bits  jit_x1_ld_add(int rd, int ra, int imm8)  in jit_x1_ld_add()  argument
477 		GX_INSN_X1_MASK) | create_Dest_X1(rd) |  in jit_x1_ld_add()
482 static tilegx_bundle_bits  jit_x0_bfexts(int rd, int ra, int bfs, int bfe)  in jit_x0_bfexts()  argument
487 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_bfexts()
492 static tilegx_bundle_bits  jit_x0_bfextu(int rd, int ra, int bfs, int bfe)  in jit_x0_bfextu()  argument
497 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_bfextu()
502 static tilegx_bundle_bits  jit_x1_addi(int rd, int ra, int imm8)  in jit_x1_addi()  argument
506 		create_Dest_X1(rd) | create_SrcA_X1(ra) |  in jit_x1_addi()
511 static tilegx_bundle_bits  jit_x0_shrui(int rd, int ra, int imm6)  in jit_x0_shrui()  argument
516 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_shrui()
521 static tilegx_bundle_bits  jit_x0_rotli(int rd, int ra, int imm6)  in jit_x0_rotli()  argument
526 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_rotli()
562 	uint64_t ra = -1, rb = -1, rd = -1, clob1 = -1, clob2 = -1, clob3 = -1;  in jit_bundle_gen()  local
678 			find_regs(bundle, &rd, &ra, &rb, &clob1, &clob2,  in jit_bundle_gen()
696 				find_regs(bundle, &rd, &ra, &rb, &clob1,  in jit_bundle_gen()
788 			find_regs(bundle, load_n_store ? (&rd) : NULL,  in jit_bundle_gen()
797 	if (check_regs(rd, ra, rb, clob1, clob2, clob3) == true)  in jit_bundle_gen()
924 				regs->regs[rd] = x;  in jit_bundle_gen()
1018 	if ((ra != rb) && (rd != TREG_SP) && !alias &&  in jit_bundle_gen()
1062 			if (rd == ra) {  in jit_bundle_gen()
1075 					jit_x1_ldna(rd, ra);  in jit_bundle_gen()
1084 					jit_x0_dblalign(rd, clob1, clob2) |  in jit_bundle_gen()
1099 					jit_x1_ldna(rd, ra);  in jit_bundle_gen()
1108 					jit_x0_dblalign(rd, clob1, ra) |  in jit_bundle_gen()
1122 							rd, rd,  in jit_bundle_gen()
1129 							rd, rd,  in jit_bundle_gen()
1137 							rd, rd,  in jit_bundle_gen()
1144 							rd, rd,  in jit_bundle_gen()
1305 			jit_x1_ldna(rd, clob2);  in jit_bundle_gen()
1310 			jit_x0_dblalign(rd, clob1, clob2) |  in jit_bundle_gen()
1330 						rd, rd,  in jit_bundle_gen()
1337 						rd, rd,  in jit_bundle_gen()
1345 						rd, rd,  in jit_bundle_gen()
1352 						rd, rd,  in jit_bundle_gen()
1377 				(int)alias, (int)rd, (int)ra,  in jit_bundle_gen()