Lines Matching refs:C
116 #define C(x) PERF_COUNT_HW_CACHE_##x macro
129 [C(L1D)] = {
130 [C(OP_READ)] = {
131 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
132 [C(RESULT_MISS)] = 0x21, /* RD_MISS */
134 [C(OP_WRITE)] = {
135 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
136 [C(RESULT_MISS)] = 0x22, /* WR_MISS */
138 [C(OP_PREFETCH)] = {
139 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
140 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
143 [C(L1I)] = {
144 [C(OP_READ)] = {
145 [C(RESULT_ACCESS)] = 0x12, /* MP_ICACHE_HIT_ISSUED */
146 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
148 [C(OP_WRITE)] = {
149 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
150 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
152 [C(OP_PREFETCH)] = {
153 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
154 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
157 [C(LL)] = {
158 [C(OP_READ)] = {
159 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
160 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
162 [C(OP_WRITE)] = {
163 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
164 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
166 [C(OP_PREFETCH)] = {
167 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
168 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
171 [C(DTLB)] = {
172 [C(OP_READ)] = {
173 [C(RESULT_ACCESS)] = 0x1d, /* TLB_CNT */
174 [C(RESULT_MISS)] = 0x20, /* TLB_EXCEPTION */
176 [C(OP_WRITE)] = {
177 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
178 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
180 [C(OP_PREFETCH)] = {
181 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
182 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
185 [C(ITLB)] = {
186 [C(OP_READ)] = {
187 [C(RESULT_ACCESS)] = 0x13, /* MP_ITLB_HIT_ISSUED */
188 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
190 [C(OP_WRITE)] = {
191 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
192 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
194 [C(OP_PREFETCH)] = {
195 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
196 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
199 [C(BPU)] = {
200 [C(OP_READ)] = {
201 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
202 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
204 [C(OP_WRITE)] = {
205 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
206 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
208 [C(OP_PREFETCH)] = {
209 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
210 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
219 [C(L1D)] = {
226 [C(OP_READ)] = {
227 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
228 [C(RESULT_MISS)] = 0x44, /* RD_MISS */
230 [C(OP_WRITE)] = {
231 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
232 [C(RESULT_MISS)] = 0x45, /* WR_MISS */
234 [C(OP_PREFETCH)] = {
235 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
236 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
239 [C(L1I)] = {
240 [C(OP_READ)] = {
241 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
242 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
244 [C(OP_WRITE)] = {
245 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
246 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
248 [C(OP_PREFETCH)] = {
249 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
250 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
253 [C(LL)] = {
254 [C(OP_READ)] = {
255 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
256 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
258 [C(OP_WRITE)] = {
259 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
260 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
262 [C(OP_PREFETCH)] = {
263 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
264 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
267 [C(DTLB)] = {
268 [C(OP_READ)] = {
269 [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
270 [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
272 [C(OP_WRITE)] = {
273 [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
274 [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
276 [C(OP_PREFETCH)] = {
277 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
278 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
281 [C(ITLB)] = {
282 [C(OP_READ)] = {
283 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
284 [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
286 [C(OP_WRITE)] = {
287 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
288 [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
290 [C(OP_PREFETCH)] = {
291 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
292 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
295 [C(BPU)] = {
296 [C(OP_READ)] = {
297 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
298 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
300 [C(OP_WRITE)] = {
301 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
302 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
304 [C(OP_PREFETCH)] = {
305 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
306 [C(RESULT_MISS)] = TILE_OP_UNSUPP,