Lines Matching refs:g2
12 sethi %hi(cheetah_fast_ecc), %g2
13 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
25 sethi %hi(cheetah_fast_ecc), %g2
26 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
38 sethi %hi(cheetah_cee), %g2
39 jmpl %g2 + %lo(cheetah_cee), %g0
51 sethi %hi(cheetah_cee), %g2
52 jmpl %g2 + %lo(cheetah_cee), %g0
64 sethi %hi(cheetah_deferred_trap), %g2
65 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
77 sethi %hi(cheetah_deferred_trap), %g2
78 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
104 rdpr %pil, %g2
146 rdpr %pil, %g2
182 mov 1, %g2 ! Setup TSTATE checking loop
184 1: wrpr %g2, %tl ! Set trap level to check
189 add %g2, 1, %g2 ! Next trap level
190 cmp %g2, %g1 ! Hit them all yet?
195 sethi %hi(dcache_parity_tl1_occurred), %g2
196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
201 mov (1 << 5), %g2 ! D-cache line size
202 sub %g1, %g2, %g1 ! Move down 1 cacheline
207 sub %g2, 8, %g3 ! 64-bit data word within line
214 subcc %g1, %g2, %g1 ! Next cacheline
233 mov 1, %g2 ! Setup TSTATE checking loop
235 1: wrpr %g2, %tl ! Set trap level to check
240 add %g2, 1, %g2 ! Next trap level
241 cmp %g2, %g1 ! Hit them all yet?
246 sethi %hi(icache_parity_tl1_occurred), %g2
247 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
249 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
252 mov (1 << 5), %g2 ! I-cache line size
253 sub %g1, %g2, %g1
257 subcc %g1, %g2, %g1
278 mov (1 << 5), %g2 ! D-cache line size
279 sub %g1, %g2, %g1
282 subcc %g1, %g2, %g1
306 sllx %g1, 63, %g2
307 or %g4, %g2, %g4
310 BRANCH_IF_JALAPENO(g2,g3,50f)
311 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
312 srlx %g2, 17, %g2
314 and %g2, 0x3ff, %g2
316 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
317 srlx %g2, 17, %g2
318 and %g2, 0x1f, %g2
320 60: sllx %g2, 9, %g2
326 add %g3, %g2, %g3
341 set 0x3ff8, %g2 /* DC_addr mask */
342 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
346 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
352 stx %g2, [%g1 + 0x20]
357 ldxa [%g2] ASI_DCACHE_UTAG, %g7
360 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
364 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
375 add %g2, %g7, %g2
376 srlx %g2, 14, %g7
384 20: set 0x1fe0, %g2 /* IC_addr mask */
385 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
386 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
390 21: ldxa [%g2] ASI_IC_TAG, %g7
397 stx %g2, [%g1 + 0x40]
399 add %g2, (1 << 3), %g2
400 ldxa [%g2] ASI_IC_TAG, %g7
401 add %g2, (1 << 3), %g2
403 ldxa [%g2] ASI_IC_TAG, %g7
404 add %g2, (1 << 3), %g2
406 ldxa [%g2] ASI_IC_TAG, %g7
408 sub %g2, (3 << 3), %g2
409 ldxa [%g2] ASI_IC_STAG, %g7
412 srlx %g2, 2, %g2
414 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
425 add %g2, %g7, %g2
426 srlx %g2, 14, %g7
434 30: andn %g5, (32 - 1), %g2
435 stx %g2, [%g1 + 0x20]
436 ldxa [%g2] ASI_EC_TAG_DATA, %g7
438 ldxa [%g2] ASI_EC_R, %g0
449 rdpr %tt, %g2
450 cmp %g2, 0x70
452 cmp %g2, 0x63
473 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
474 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
475 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
490 rdpr %pil, %g2
509 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
510 andn %g2, ESTATE_ERROR_CEEN, %g2
511 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
526 rdpr %pil, %g2
545 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
546 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
547 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
562 rdpr %pil, %g2