62 #define REG_W0		(__MAX_BPF_REG+0)	/* Work register 1 (even) */  macro
67 #define REG_0		REG_W0			/* Register 0 */
94 	[REG_W0]	= 0,
615 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
623 		EMIT4_IMM(0xa7080000, REG_W0, 0);  in bpf_jit_insn()
627 		EMIT4(0xb9970000, REG_W0, src_reg);  in bpf_jit_insn()
635 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
643 		EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
647 		EMIT4(0xb9870000, REG_W0, src_reg);  in bpf_jit_insn()
655 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
664 		EMIT4_IMM(0xa7080000, REG_W0, 0);  in bpf_jit_insn()
668 		EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,  in bpf_jit_insn()
677 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
686 		EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
690 		EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,  in bpf_jit_insn()
904 		EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);  in bpf_jit_insn()
906 		EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
911 		EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);  in bpf_jit_insn()
913 		EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
918 		EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);  in bpf_jit_insn()
920 		EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
925 		EMIT6_IMM(0xc0010000, REG_W0, imm);  in bpf_jit_insn()
927 		EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
935 		EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,  in bpf_jit_insn()
941 		EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,  in bpf_jit_insn()
1027 		EMIT4_IMM(0xa7080000, REG_W0, 1);  in bpf_jit_insn()
1029 		EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);  in bpf_jit_insn()