Lines Matching refs:r5

23 	basr	%r5,0
24 0:	al	%r5,21f-0b(%r5)			/* get &_vdso_data */
35 1:	l	%r4,__VDSO_UPD_COUNT+4(%r5)	/* load update counter */
40 	s	%r0,__VDSO_XTIME_STAMP(%r5)	/* TOD - cycle_last */
41 	sl	%r1,__VDSO_XTIME_STAMP+4(%r5)
44 2:	ms	%r0,__VDSO_TK_MULT(%r5)		/*  * tk->mult */
46 	l	%r0,__VDSO_TK_MULT(%r5)
50 	a	%r0,__VDSO_TK_MULT(%r5)
52 	al	%r0,__VDSO_WTOM_NSEC(%r5)
53 	al	%r1,__VDSO_WTOM_NSEC+4(%r5)
56 5:	l	%r2,__VDSO_TK_SHIFT(%r5)	/* Timekeeper shift */
58 	l	%r2,__VDSO_WTOM_SEC+4(%r5)
59 	cl	%r4,__VDSO_UPD_COUNT+4(%r5)	/* check update counter */
61 	basr	%r5,0
64 	cl	%r1,20f-6b(%r5)
67 	sl	%r1,20f-6b(%r5)
78 9:	l	%r4,__VDSO_UPD_COUNT+4(%r5)	/* load update counter */
81 	l	%r2,__VDSO_WTOM_CRS_SEC+4(%r5)
82 	l	%r1,__VDSO_WTOM_CRS_NSEC+4(%r5)
83 	cl	%r4,__VDSO_UPD_COUNT+4(%r5)	/* check update counter */
88 10:	l	%r4,__VDSO_UPD_COUNT+4(%r5)	/* load update counter */
91 	l	%r2,__VDSO_XTIME_CRS_SEC+4(%r5)
92 	l	%r1,__VDSO_XTIME_CRS_NSEC+4(%r5)
93 	cl	%r4,__VDSO_UPD_COUNT+4(%r5)	/* check update counter */
98 11:	l	%r4,__VDSO_UPD_COUNT+4(%r5)	/* load update counter */
103 	s	%r0,__VDSO_XTIME_STAMP(%r5)	/* TOD - cycle_last */
104 	sl	%r1,__VDSO_XTIME_STAMP+4(%r5)
107 12:	ms	%r0,__VDSO_TK_MULT(%r5)		/*  * tk->mult */
109 	l	%r0,__VDSO_TK_MULT(%r5)
113 	a	%r0,__VDSO_TK_MULT(%r5)
115 	al	%r0,__VDSO_XTIME_NSEC(%r5)	/*  + tk->xtime_nsec */
116 	al	%r1,__VDSO_XTIME_NSEC+4(%r5)
119 14:	l	%r2,__VDSO_TK_SHIFT(%r5)	/* Timekeeper shift */
121 	l	%r2,__VDSO_XTIME_SEC+4(%r5)
122 	cl	%r4,__VDSO_UPD_COUNT+4(%r5)	/* check update counter */
124 	basr	%r5,0
127 	cl	%r1,20f-15b(%r5)
130 	sl	%r1,20f-15b(%r5)