Lines Matching refs:load
107 2: lg %r15,__LC_ASYNC_STACK # load async stack
188 lg %r15,__THREAD_ksp(%r1) # load kernel stack of next
189 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
191 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
210 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
212 brasl %r14,load_fpu_regs # load guest fp/vx regs
214 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
218 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
229 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
240 lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
356 # _CIF_ASCE is set, load user space asce
360 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
378 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
381 llgh %r1,__PT_INT_CODE+2(%r11) # load new svc number
520 lgf %r1,0(%r10,%r1) # load address of handler routine
674 # _CIF_ASCE is set, load user space asce
678 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
836 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
953 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1049 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1066 0: # check if base register setup + TIF bit load has been done