Lines Matching refs:X
1662 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) macro
1668 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1704 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1714 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1718 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1722 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1731 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1798 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1803 …(X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << …
1935 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
3057 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3321 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3322 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3353 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3354 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3384 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3385 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3386 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3390 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3391 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3393 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3395 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3397 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3398 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3400 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3401 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3422 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3424 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3428 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3429 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3440 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3442 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3444 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3445 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3447 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3449 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3471 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3482 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3484 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3486 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3489 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3491 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3493 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3495 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3507 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3509 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3511 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3513 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3520 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3522 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3524 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3526 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3546 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3550 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3552 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3554 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3558 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3559 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3563 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3571 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3573 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3575 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3576 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3578 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3580 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3582 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3583 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3588 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3590 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3610 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3614 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3622 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3624 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3658 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3659 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3660 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3662 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3664 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3669 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3671 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3673 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3689 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3691 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3696 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3698 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3703 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3705 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3707 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3708 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3710 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3712 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3717 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3753 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3760 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3805 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3949 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3951 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3956 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3958 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3963 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3975 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3977 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3979 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3981 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3983 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3985 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3993 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3995 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3997 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3999 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4001 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4003 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4005 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4007 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4009 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4011 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4019 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4021 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4023 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4025 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4027 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4068 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4238 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4240 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4245 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4247 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4249 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4251 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4273 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4275 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4277 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4281 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4283 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4284 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4286 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4288 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4290 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4291 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4293 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4294 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4296 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4312 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4314 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4316 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4318 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4320 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4322 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4324 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4326 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4327 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4331 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4332 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4333 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4335 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4337 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4341 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4343 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4345 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4347 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4349 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4351 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4353 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4354 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4356 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4357 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4359 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4367 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4369 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4371 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4376 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4378 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4379 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4381 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4389 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4393 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4395 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4400 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4402 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4404 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4405 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4407 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4409 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4419 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4421 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4422 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4424 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4426 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4436 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4438 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4440 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4441 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4443 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4445 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4452 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4454 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4456 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4469 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4471 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4475 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4477 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4485 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4487 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4491 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4492 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4494 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4496 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4498 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4503 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4505 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4506 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4508 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4510 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4513 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4514 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4516 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4518 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4519 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4520 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4521 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4522 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4523 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4524 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4525 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4526 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4527 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4528 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4529 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4532 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4533 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4534 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4535 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4536 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4539 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4681 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4683 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4708 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4710 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4749 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4825 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4839 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4859 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4867 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4907 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4909 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },