Lines Matching refs:RA0
379 #define RA0 RA + 1 macro
384 #define RAQ RA0 + 1
2541 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2542 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2543 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2544 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2548 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2549 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2550 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3393 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3395 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3400 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3424 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3486 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3491 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3495 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3520 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3554 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3556 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3558 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3561 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3563 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3583 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3612 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3614 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3622 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3698 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3705 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3708 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3951 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3956 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3958 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3997 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4019 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4288 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4290 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4293 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4296 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4312 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4314 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4326 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4327 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4335 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4337 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4351 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4353 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4354 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4356 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4357 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4359 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4367 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4369 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4378 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4379 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4381 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4389 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4407 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4409 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4419 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4421 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4422 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4426 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4438 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4443 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4445 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4454 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4456 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4469 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4471 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4477 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4494 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4498 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4506 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4510 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4532 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4533 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4534 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4535 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4536 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4539 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4541 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4542 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4545 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4547 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4551 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4552 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4555 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4557 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4561 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4565 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4569 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4574 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4576 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4577 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4579 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4583 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4587 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4591 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4597 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4599 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4601 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4603 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4605 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4607 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4609 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4611 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4613 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4615 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4618 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4622 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4728 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4730 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4731 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4732 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4734 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4736 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4738 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4740 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4743 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4747 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },