48 	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);  in qe_gpio_save_regs()  local
51 	qe_gc->cpdata = in_be32(&regs->cpdata);  in qe_gpio_save_regs()
52 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;  in qe_gpio_save_regs()
53 	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);  in qe_gpio_save_regs()
54 	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);  in qe_gpio_save_regs()
55 	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);  in qe_gpio_save_regs()
56 	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);  in qe_gpio_save_regs()
57 	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);  in qe_gpio_save_regs()
72 	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);  in qe_gpio_set()  local
77 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set()
80 		qe_gc->cpdata |= pin_mask;  in qe_gpio_set()
82 		qe_gc->cpdata &= ~pin_mask;  in qe_gpio_set()
84 	out_be32(&regs->cpdata, qe_gc->cpdata);  in qe_gpio_set()
86 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set()
92 	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);  in qe_gpio_dir_in()  local
95 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_in()
99 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_in()
107 	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);  in qe_gpio_dir_out()  local
112 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_out()
116 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_out()
144 	struct qe_gpio_chip *qe_gc;  in qe_pin_request()  local
168 	qe_gc = to_qe_gpio_chip(mm_gc);  in qe_pin_request()
170 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_request()
173 	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {  in qe_pin_request()
174 		qe_pin->controller = qe_gc;  in qe_pin_request()
181 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_request()
202 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_free()  local
206 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_free()
207 	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);  in qe_pin_free()
208 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_free()
224 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_dedicated()  local
225 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_dedicated()
226 	struct qe_pio_regs *sregs = &qe_gc->saved_regs;  in qe_pin_set_dedicated()
233 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
244 		qe_gc->cpdata |= mask1;  in qe_pin_set_dedicated()
246 		qe_gc->cpdata &= ~mask1;  in qe_pin_set_dedicated()
248 	out_be32(&regs->cpdata, qe_gc->cpdata);  in qe_pin_set_dedicated()
251 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
264 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_gpio()  local
265 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_gpio()
268 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_gpio()
273 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_gpio()
283 		struct qe_gpio_chip *qe_gc;  in qe_add_gpiochips()  local
287 		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);  in qe_add_gpiochips()
288 		if (!qe_gc) {  in qe_add_gpiochips()
293 		spin_lock_init(&qe_gc->lock);  in qe_add_gpiochips()
295 		mm_gc = &qe_gc->mm_gc;  in qe_add_gpiochips()
312 		kfree(qe_gc);  in qe_add_gpiochips()