119 struct spu_pdata {  struct
128 static struct spu_pdata *spu_pdata(struct spu *spu)  in spu_pdata()  argument
148 	return spu_pdata(arg)->spe_id;  in ps3_get_spe_id()
171 		&spu_pdata(spu)->priv2_addr, &problem_phys,  in construct_spu()
173 		&spu_pdata(spu)->shadow_addr,  in construct_spu()
174 		&spu_pdata(spu)->spe_id);  in construct_spu()
192 	iounmap(spu_pdata(spu)->shadow);  in spu_unmap()
210 	spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,  in setup_areas()
213 	if (!spu_pdata(spu)->shadow) {  in setup_areas()
235 	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,  in setup_areas()
243 	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,  in setup_areas()
245 		spu_pdata(spu)->shadow_addr);  in setup_areas()
246 	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,  in setup_areas()
248 		(unsigned long)spu_pdata(spu)->shadow);  in setup_areas()
262 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
268 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
274 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
295 	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,  in enable_spu()
296 		spu_pdata(spu)->resource_id);  in enable_spu()
319 	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);  in enable_spu()
330 	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);  in ps3_destroy_spu()
341 	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);  in ps3_destroy_spu()
356 	spu->pdata = kzalloc(sizeof(struct spu_pdata),  in ps3_create_spu()
364 	spu_pdata(spu)->resource_id = (unsigned long)data;  in ps3_create_spu()
368 	spu_pdata(spu)->cache.sr1 = 0x33;  in ps3_create_spu()
385 	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)  in ps3_create_spu()
498 	spu_pdata(spu)->cache.masks[class] = mask;  in int_mask_set()
499 	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,  in int_mask_set()
500 		spu_pdata(spu)->cache.masks[class]);  in int_mask_set()
505 	return spu_pdata(spu)->cache.masks[class];  in int_mask_get()
512 	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,  in int_stat_clear()
520 	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);  in int_stat_get()
531 	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);  in mfc_dar_get()
541 	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);  in mfc_dsisr_get()
556 	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));  in mfc_sr1_set()
558 	spu_pdata(spu)->cache.sr1 = sr1;  in mfc_sr1_set()
560 		spu_pdata(spu)->spe_id,  in mfc_sr1_set()
562 		spu_pdata(spu)->cache.sr1);  in mfc_sr1_set()
567 	return spu_pdata(spu)->cache.sr1;  in mfc_sr1_get()
572 	spu_pdata(spu)->cache.tclass_id = tclass_id;  in mfc_tclass_id_set()
574 		spu_pdata(spu)->spe_id,  in mfc_tclass_id_set()
576 		spu_pdata(spu)->cache.tclass_id);  in mfc_tclass_id_set()
581 	return spu_pdata(spu)->cache.tclass_id;  in mfc_tclass_id_get()