110 	struct eeh_pe *pe;  in pnv_eeh_ei_write()  local
136 	pe = eeh_pe_get(edev);  in pnv_eeh_ei_write()
138 	if (!pe)  in pnv_eeh_ei_write()
142 	ret = eeh_ops->err_inject(pe, type, func, addr, mask);  in pnv_eeh_ei_write()
378 	if (!edev || edev->pe)  in pnv_eeh_probe()
439 		edev->pe->state |= EEH_PE_CFG_RESTRICTED;  in pnv_eeh_probe()
447 	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {  in pnv_eeh_probe()
448 		edev->pe->bus = pci_find_bus(hose->global_number,  in pnv_eeh_probe()
450 		if (edev->pe->bus)  in pnv_eeh_probe()
451 			edev->pe->state |= EEH_PE_PRI_BUS;  in pnv_eeh_probe()
475 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)  in pnv_eeh_set_option()  argument
477 	struct pci_controller *hose = pe->phb;  in pnv_eeh_set_option()
506 			phb->freeze_pe(phb, pe->addr);  in pnv_eeh_set_option()
510 		rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);  in pnv_eeh_set_option()
514 				pe->addr);  in pnv_eeh_set_option()
523 		return phb->unfreeze_pe(phb, pe->addr, opt);  in pnv_eeh_set_option()
525 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);  in pnv_eeh_set_option()
529 			pe->addr);  in pnv_eeh_set_option()
543 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)  in pnv_eeh_get_pe_addr()  argument
545 	return pe->addr;  in pnv_eeh_get_pe_addr()
548 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)  in pnv_eeh_get_phb_diag()  argument
550 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_phb_diag()
553 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,  in pnv_eeh_get_phb_diag()
557 			__func__, rc, pe->phb->global_number);  in pnv_eeh_get_phb_diag()
560 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)  in pnv_eeh_get_phb_state()  argument
562 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_phb_state()
569 					pe->addr,  in pnv_eeh_get_phb_state()
588 	} else if (!(pe->state & EEH_PE_ISOLATED)) {  in pnv_eeh_get_phb_state()
589 		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);  in pnv_eeh_get_phb_state()
590 		pnv_eeh_get_phb_diag(pe);  in pnv_eeh_get_phb_state()
593 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_phb_state()
599 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)  in pnv_eeh_get_pe_state()  argument
601 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_pe_state()
613 	if (pe->state & EEH_PE_RESET) {  in pnv_eeh_get_pe_state()
626 		fstate = phb->get_pe_state(phb, pe->addr);  in pnv_eeh_get_pe_state()
629 						pe->addr,  in pnv_eeh_get_pe_state()
636 				pe->addr);  in pnv_eeh_get_pe_state()
673 			pe->addr, fstate);  in pnv_eeh_get_pe_state()
687 	    !(pe->state & EEH_PE_ISOLATED)) {  in pnv_eeh_get_pe_state()
689 			phb->freeze_pe(phb, pe->addr);  in pnv_eeh_get_pe_state()
691 		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);  in pnv_eeh_get_pe_state()
692 		pnv_eeh_get_phb_diag(pe);  in pnv_eeh_get_pe_state()
695 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_pe_state()
711 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)  in pnv_eeh_get_state()  argument
715 	if (pe->type & EEH_PE_PHB)  in pnv_eeh_get_state()
716 		ret = pnv_eeh_get_phb_state(pe);  in pnv_eeh_get_state()
718 		ret = pnv_eeh_get_pe_state(pe);  in pnv_eeh_get_state()
910 static int pnv_eeh_reset(struct eeh_pe *pe, int option)  in pnv_eeh_reset()  argument
912 	struct pci_controller *hose = pe->phb;  in pnv_eeh_reset()
930 	if (pe->type & EEH_PE_PHB) {  in pnv_eeh_reset()
958 		bus = eeh_pe_bus_get(pe);  in pnv_eeh_reset()
977 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)  in pnv_eeh_wait_state()  argument
983 		ret = pnv_eeh_get_state(pe, &mwait);  in pnv_eeh_wait_state()
995 				__func__, pe->addr, max_wait);  in pnv_eeh_wait_state()
1015 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,  in pnv_eeh_get_log()  argument
1019 		pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_log()
1032 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)  in pnv_eeh_configure_bridge()  argument
1049 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,  in pnv_eeh_err_inject()  argument
1052 	struct pci_controller *hose = pe->phb;  in pnv_eeh_err_inject()
1078 	rc = opal_pci_err_inject(phb->opal_id, pe->addr,  in pnv_eeh_err_inject()
1084 			hose->global_number, pe->addr);  in pnv_eeh_err_inject()
1095 	if (!edev || !edev->pe)  in pnv_eeh_cfg_blocked()
1098 	if (edev->pe->state & EEH_PE_CFG_BLOCKED)  in pnv_eeh_cfg_blocked()
1211 			  u16 pe_no, struct eeh_pe **pe)  in pnv_eeh_get_pe()  argument
1240 	*pe = dev_pe;  in pnv_eeh_get_pe()
1262 		*pe = dev_pe;  in pnv_eeh_get_pe()
1283 static int pnv_eeh_next_error(struct eeh_pe **pe)  in pnv_eeh_next_error()  argument
1352 				*pe = phb_pe;  in pnv_eeh_next_error()
1360 				*pe = phb_pe;  in pnv_eeh_next_error()
1383 				be64_to_cpu(frozen_pe_no), pe)) {  in pnv_eeh_next_error()
1401 			} else if ((*pe)->state & EEH_PE_ISOLATED ||  in pnv_eeh_next_error()
1402 				   eeh_pe_passed(*pe)) {  in pnv_eeh_next_error()
1407 				       (*pe)->addr,  in pnv_eeh_next_error()
1408 					(*pe)->phb->global_number);  in pnv_eeh_next_error()
1411 				       eeh_pe_loc_get(*pe),  in pnv_eeh_next_error()
1431 		    !((*pe)->state & EEH_PE_ISOLATED)) {  in pnv_eeh_next_error()
1432 			eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);  in pnv_eeh_next_error()
1433 			pnv_eeh_get_phb_diag(*pe);  in pnv_eeh_next_error()
1436 				pnv_pci_dump_phb_diag_data((*pe)->phb,  in pnv_eeh_next_error()
1437 							   (*pe)->data);  in pnv_eeh_next_error()
1445 			parent_pe = (*pe)->parent;  in pnv_eeh_next_error()
1455 					*pe = parent_pe;  in pnv_eeh_next_error()
1462 			eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);  in pnv_eeh_next_error()