168 	unsigned long		fcr;  in ohare_htw_scc_enable()  local
194 		fcr = MACIO_IN32(OHARE_FCR);  in ohare_htw_scc_enable()
196 		if (!(fcr & OH_SCC_ENABLE)) {  in ohare_htw_scc_enable()
197 			fcr |= OH_SCC_ENABLE;  in ohare_htw_scc_enable()
205 					fcr &= ~HRW_SCC_TRANS_EN_N;  in ohare_htw_scc_enable()
206 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
207 				fcr |= (rmask = HRW_RESET_SCC);  in ohare_htw_scc_enable()
208 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
210 				fcr |= (rmask = OH_SCC_RESET);  in ohare_htw_scc_enable()
211 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
217 			fcr &= ~rmask;  in ohare_htw_scc_enable()
218 			MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
221 			fcr |= OH_SCCA_IO;  in ohare_htw_scc_enable()
223 			fcr |= OH_SCCB_IO;  in ohare_htw_scc_enable()
224 		MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
233 		fcr = MACIO_IN32(OHARE_FCR);  in ohare_htw_scc_enable()
235 			fcr &= ~OH_SCCA_IO;  in ohare_htw_scc_enable()
237 			fcr &= ~OH_SCCB_IO;  in ohare_htw_scc_enable()
238 		MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
239 		if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {  in ohare_htw_scc_enable()
240 			fcr &= ~OH_SCC_ENABLE;  in ohare_htw_scc_enable()
242 				fcr |= HRW_SCC_TRANS_EN_N;  in ohare_htw_scc_enable()
243 			MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
608 	u32			fcr;  in core99_scc_enable()  local
625 		fcr = MACIO_IN32(KEYLARGO_FCR0);  in core99_scc_enable()
627 		if (!(fcr & KL0_SCC_CELL_ENABLE)) {  in core99_scc_enable()
628 			fcr |= KL0_SCC_CELL_ENABLE;  in core99_scc_enable()
632 			fcr |= KL0_SCCA_ENABLE;  in core99_scc_enable()
635 				fcr &= ~KL0_SCC_A_INTF_ENABLE;  in core99_scc_enable()
637 				fcr |= KL0_SCC_A_INTF_ENABLE;  in core99_scc_enable()
640 			fcr |= KL0_SCCB_ENABLE;  in core99_scc_enable()
643 				fcr &= ~KL0_SCC_B_INTF_ENABLE;  in core99_scc_enable()
644 				fcr |= KL0_IRDA_ENABLE;  in core99_scc_enable()
645 				fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;  in core99_scc_enable()
646 				fcr |= KL0_IRDA_SOURCE1_SEL;  in core99_scc_enable()
647 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);  in core99_scc_enable()
648 				fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);  in core99_scc_enable()
651 				fcr |= KL0_SCC_B_INTF_ENABLE;  in core99_scc_enable()
653 		MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()
678 		fcr = MACIO_IN32(KEYLARGO_FCR0);  in core99_scc_enable()
680 			fcr &= ~KL0_SCCA_ENABLE;  in core99_scc_enable()
682 			fcr &= ~KL0_SCCB_ENABLE;  in core99_scc_enable()
685 				fcr &= ~KL0_IRDA_ENABLE;  in core99_scc_enable()
686 				fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);  in core99_scc_enable()
687 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);  in core99_scc_enable()
688 				fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);  in core99_scc_enable()
691 		MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()
692 		if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {  in core99_scc_enable()
693 			fcr &= ~KL0_SCC_CELL_ENABLE;  in core99_scc_enable()
694 			MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()