Lines Matching refs:r3
74 mfpvr r3
75 srwi r3,r3,16
76 cmplwi cr0,r3,0x7000
89 mfspr r3,SPRN_HID0
90 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
91 mtspr SPRN_HID0,r3
94 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
97 mtspr SPRN_HID0,r3
98 xori r3,r3,(HID0_DCI|HID0_ICFI)
99 mtspr SPRN_HID0,r3
105 oris r3,r5,L2CR_L2DO@h
109 1: mtspr SPRN_L2CR,r3
160 1: mfspr r3,SPRN_L2CR
161 rlwinm. r0,r3,0,31,31
250 lis r3,0xfff0 /* read from ROM for displacement flush */
258 2: lwz r0,0(r3) /* touch each cache line */
259 addi r3,r3,32
274 mfspr r3,SPRN_L2CR
275 cmpwi r3,0 /* check if it is enabled first */
277 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
291 ori r0,r3,L2CR_L2HWF_745x
298 rlwinm r3,r3,0,~L2CR_L2E
302 1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
312 oris r4,r3,L2CR_L2I@h
323 4: mfspr r3,SPRN_L3CR
324 cmpwi r3,0 /* check if it is enabled */
326 oris r0,r3,L3CR_L3IO@h
338 rlwinm r3,r3,0,~L3CR_L3E
340 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
342 ori r4,r3,L3CR_L3I