Lines Matching refs:r0
47 rlwinm r0,r11,0,~MSR_EE
48 rlwinm r0,r0,0,~MSR_DR
50 mtmsr r0
82 1: lwz r0,0(r4)
124 1: lwz r0,0(r4)
161 rlwinm. r0,r3,0,31,31
171 mfspr r0,SPRN_HID0
172 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
173 mtspr SPRN_HID0,r0
179 mfspr r0,SPRN_HID0
180 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
181 mtspr SPRN_HID0,r0
196 rlwinm r0,r11,0,~MSR_EE
197 rlwinm r0,r0,0,~MSR_DR
199 mtmsr r0
207 mfspr r0,SPRN_MSSCR0
208 rlwinm r0,r0,0,0,29
209 mtspr SPRN_MSSCR0,r0
233 lwz r0,0(r4)
258 2: lwz r0,0(r3) /* touch each cache line */
277 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
281 1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
291 ori r0,r3,L2CR_L2HWF_745x
293 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
294 3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
295 andi. r0,r0,L2CR_L2HWF_745x
317 andis. r0,r4,L2CR_L2I@h
326 oris r0,r3,L3CR_L3IO@h
327 ori r0,r0,L3CR_L3DO
329 mtspr SPRN_L3CR,r0 /* lock the L3 cache */
332 ori r0,r0,L3CR_L3HWF
334 mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
335 5: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
336 andi. r0,r0,L3CR_L3HWF
345 andi. r0,r4,L3CR_L3I
350 6: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
351 rlwinm r0,r0,0,~HID0_DCE
352 mtspr SPRN_HID0,r0