100 				       u8 bus, u8 dev_fn, u8 offset)  in u3_agp_cfg_access()  argument
107 		caddr = u3_agp_cfa0(dev_fn, offset);  in u3_agp_cfg_access()
109 		caddr = u3_agp_cfa1(bus, dev_fn, offset);  in u3_agp_cfg_access()
116 	offset &= 0x07;  in u3_agp_cfg_access()
117 	return hose->cfg_data + offset;  in u3_agp_cfg_access()
121 			      int offset, int len, u32 *val)  in u3_agp_read_config()  argument
130 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_read_config()
152 			       int offset, int len, u32 val)  in u3_agp_write_config()  argument
161 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_write_config()
199 				      u8 bus, u8 devfn, u8 offset)  in u3_ht_cfg_access()  argument
204 		return hose->cfg_data + u3_ht_cfa0(devfn, offset);  in u3_ht_cfg_access()
206 		return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);  in u3_ht_cfg_access()
209 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_read_config()  argument
215 	addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));  in u3_ht_root_read_config()
232 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_write_config()  argument
237 	addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));  in u3_ht_root_write_config()
239 	if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)  in u3_ht_root_write_config()
258 			     int offset, int len, u32 *val)  in u3_ht_read_config()  argument
268 		return u3_ht_root_read_config(hose, offset, len, val);  in u3_ht_read_config()
270 	if (offset > 0xff)  in u3_ht_read_config()
273 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_read_config()
296 			      int offset, int len, u32 val)  in u3_ht_write_config()  argument
306 		return u3_ht_root_write_config(hose, offset, len, val);  in u3_ht_write_config()
308 	if (offset > 0xff)  in u3_ht_write_config()
311 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_write_config()
356                                         u8 bus, u8 dev_fn, int offset)  in u4_pcie_cfg_access()  argument
361                 caddr = u4_pcie_cfa0(dev_fn, offset);  in u4_pcie_cfg_access()
363                 caddr = u4_pcie_cfa1(bus, dev_fn, offset);  in u4_pcie_cfg_access()
370         offset &= 0x03;  in u4_pcie_cfg_access()
371         return hose->cfg_data + offset;  in u4_pcie_cfg_access()
375                                int offset, int len, u32 *val)  in u4_pcie_read_config()  argument
383         if (offset >= 0x1000)  in u4_pcie_read_config()
385         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_read_config()
406                                 int offset, int len, u32 val)  in u4_pcie_write_config()  argument
414         if (offset >= 0x1000)  in u4_pcie_write_config()
416         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_write_config()