Lines Matching refs:priv2
183 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_cntl() local
188 switch (in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
191 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
197 csa->priv2.mfc_control_RW = in save_mfc_cntl()
198 in_be64(&priv2->mfc_control_RW) | in save_mfc_cntl()
202 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in save_mfc_cntl()
203 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
207 csa->priv2.mfc_control_RW = in save_mfc_cntl()
208 in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
263 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_stopped_status() local
273 csa->priv2.mfc_control_RW &= ~mask; in save_mfc_stopped_status()
274 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask; in save_mfc_stopped_status()
279 struct spu_priv2 __iomem *priv2 = spu->priv2; in halt_mfc_decr() local
285 out_be64(&priv2->mfc_control_RW, in halt_mfc_decr()
349 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_queues() local
356 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) { in save_mfc_queues()
358 csa->priv2.puq[i].mfc_cq_data0_RW = in save_mfc_queues()
359 in_be64(&priv2->puq[i].mfc_cq_data0_RW); in save_mfc_queues()
360 csa->priv2.puq[i].mfc_cq_data1_RW = in save_mfc_queues()
361 in_be64(&priv2->puq[i].mfc_cq_data1_RW); in save_mfc_queues()
362 csa->priv2.puq[i].mfc_cq_data2_RW = in save_mfc_queues()
363 in_be64(&priv2->puq[i].mfc_cq_data2_RW); in save_mfc_queues()
364 csa->priv2.puq[i].mfc_cq_data3_RW = in save_mfc_queues()
365 in_be64(&priv2->puq[i].mfc_cq_data3_RW); in save_mfc_queues()
368 csa->priv2.spuq[i].mfc_cq_data0_RW = in save_mfc_queues()
369 in_be64(&priv2->spuq[i].mfc_cq_data0_RW); in save_mfc_queues()
370 csa->priv2.spuq[i].mfc_cq_data1_RW = in save_mfc_queues()
371 in_be64(&priv2->spuq[i].mfc_cq_data1_RW); in save_mfc_queues()
372 csa->priv2.spuq[i].mfc_cq_data2_RW = in save_mfc_queues()
373 in_be64(&priv2->spuq[i].mfc_cq_data2_RW); in save_mfc_queues()
374 csa->priv2.spuq[i].mfc_cq_data3_RW = in save_mfc_queues()
375 in_be64(&priv2->spuq[i].mfc_cq_data3_RW); in save_mfc_queues()
417 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_tsq() local
423 csa->priv2.spu_tag_status_query_RW = in save_mfc_csr_tsq()
424 in_be64(&priv2->spu_tag_status_query_RW); in save_mfc_csr_tsq()
429 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_cmd() local
435 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW); in save_mfc_csr_cmd()
436 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW); in save_mfc_csr_cmd()
441 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_ato() local
447 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW); in save_mfc_csr_ato()
472 struct spu_priv2 __iomem *priv2 = spu->priv2; in purge_mfc_queue() local
478 out_be64(&priv2->mfc_control_RW, in purge_mfc_queue()
486 struct spu_priv2 __iomem *priv2 = spu->priv2; in wait_purge_complete() local
492 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in wait_purge_complete()
527 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_privcntl() local
532 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW); in save_spu_privcntl()
537 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_spu_privcntl() local
543 out_be64(&priv2->spu_privcntl_RW, 0UL); in reset_spu_privcntl()
549 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_lslr() local
554 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW); in save_spu_lslr()
559 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_spu_lslr() local
565 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK); in reset_spu_lslr()
571 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_cfg() local
576 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW); in save_spu_cfg()
621 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_ppuint_mb() local
626 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R); in save_ppuint_mb()
631 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_ch_part1() local
639 out_be64(&priv2->spu_chnlcntptr_RW, 1); in save_ch_part1()
640 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
645 out_be64(&priv2->spu_chnlcntptr_RW, idx); in save_ch_part1()
647 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
648 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW); in save_ch_part1()
649 out_be64(&priv2->spu_chnldata_RW, 0UL); in save_ch_part1()
650 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_ch_part1()
657 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_mb() local
663 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); in save_spu_mb()
665 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW); in save_spu_mb()
667 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW); in save_spu_mb()
669 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_spu_mb()
675 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_cmd() local
680 out_be64(&priv2->spu_chnlcntptr_RW, 21UL); in save_mfc_cmd()
682 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW); in save_mfc_cmd()
688 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch() local
699 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch()
701 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in reset_ch()
708 struct spu_priv2 __iomem *priv2 = spu->priv2; in resume_mfc_queue() local
714 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE); in resume_mfc_queue()
750 csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; in set_switch_active()
978 struct spu_priv2 __iomem *priv2 = spu->priv2; in suspend_mfc_and_halt_decr() local
984 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE | in suspend_mfc_and_halt_decr()
992 struct spu_priv2 __iomem *priv2 = spu->priv2; in wait_suspend_mfc_complete() local
998 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in wait_suspend_mfc_complete()
1081 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch_part1() local
1090 out_be64(&priv2->spu_chnlcntptr_RW, 1); in reset_ch_part1()
1091 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1096 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch_part1()
1098 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1099 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in reset_ch_part1()
1106 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch_part2() local
1117 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch_part2()
1119 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in reset_ch_part2()
1277 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) { in setup_decr()
1306 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R; in setup_ppuint_mb()
1326 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_privcntl() local
1331 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW); in restore_spu_privcntl()
1400 struct spu_priv2 __iomem *priv2 = spu->priv2; in suspend_mfc() local
1406 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in suspend_mfc()
1432 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_queues() local
1439 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) { in restore_mfc_queues()
1441 out_be64(&priv2->puq[i].mfc_cq_data0_RW, in restore_mfc_queues()
1442 csa->priv2.puq[i].mfc_cq_data0_RW); in restore_mfc_queues()
1443 out_be64(&priv2->puq[i].mfc_cq_data1_RW, in restore_mfc_queues()
1444 csa->priv2.puq[i].mfc_cq_data1_RW); in restore_mfc_queues()
1445 out_be64(&priv2->puq[i].mfc_cq_data2_RW, in restore_mfc_queues()
1446 csa->priv2.puq[i].mfc_cq_data2_RW); in restore_mfc_queues()
1447 out_be64(&priv2->puq[i].mfc_cq_data3_RW, in restore_mfc_queues()
1448 csa->priv2.puq[i].mfc_cq_data3_RW); in restore_mfc_queues()
1451 out_be64(&priv2->spuq[i].mfc_cq_data0_RW, in restore_mfc_queues()
1452 csa->priv2.spuq[i].mfc_cq_data0_RW); in restore_mfc_queues()
1453 out_be64(&priv2->spuq[i].mfc_cq_data1_RW, in restore_mfc_queues()
1454 csa->priv2.spuq[i].mfc_cq_data1_RW); in restore_mfc_queues()
1455 out_be64(&priv2->spuq[i].mfc_cq_data2_RW, in restore_mfc_queues()
1456 csa->priv2.spuq[i].mfc_cq_data2_RW); in restore_mfc_queues()
1457 out_be64(&priv2->spuq[i].mfc_cq_data3_RW, in restore_mfc_queues()
1458 csa->priv2.spuq[i].mfc_cq_data3_RW); in restore_mfc_queues()
1488 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_tsq() local
1493 out_be64(&priv2->spu_tag_status_query_RW, in restore_mfc_csr_tsq()
1494 csa->priv2.spu_tag_status_query_RW); in restore_mfc_csr_tsq()
1500 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_cmd() local
1506 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW); in restore_mfc_csr_cmd()
1507 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW); in restore_mfc_csr_cmd()
1513 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_ato() local
1518 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW); in restore_mfc_csr_ato()
1573 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_ch_part1() local
1582 out_be64(&priv2->spu_chnlcntptr_RW, idx); in restore_ch_part1()
1584 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]); in restore_ch_part1()
1585 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]); in restore_ch_part1()
1592 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_ch_part2() local
1606 out_be64(&priv2->spu_chnlcntptr_RW, idx); in restore_ch_part2()
1608 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in restore_ch_part2()
1615 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_lslr() local
1620 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW); in restore_spu_lslr()
1626 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_cfg() local
1631 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW); in restore_spu_cfg()
1656 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_mb() local
1662 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); in restore_spu_mb()
1664 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]); in restore_spu_mb()
1666 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]); in restore_spu_mb()
1688 struct spu_priv2 __iomem *priv2 = spu->priv2; in check_ppuint_mb_stat() local
1696 dummy = in_be64(&priv2->puint_mb_R); in check_ppuint_mb_stat()
1743 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_cntl() local
1748 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW); in restore_mfc_cntl()
1890 struct spu_priv2 __iomem *priv2 = spu->priv2; in force_spu_isolate_exit() local
1902 out_be64(&priv2->spu_privcntl_RW, 4LL); in force_spu_isolate_exit()
1910 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL); in force_spu_isolate_exit()
2181 csa->priv2.spu_lslr_RW = LS_ADDR_MASK; in init_priv2()
2182 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE | in init_priv2()