39 	struct spu *spu = ctx->spu;  in spu_hw_mbox_read()  local
40 	struct spu_problem __iomem *prob = spu->problem;  in spu_hw_mbox_read()
44 	spin_lock_irq(&spu->register_lock);  in spu_hw_mbox_read()
50 	spin_unlock_irq(&spu->register_lock);  in spu_hw_mbox_read()
56 	return in_be32(&ctx->spu->problem->mb_stat_R);  in spu_hw_mbox_stat_read()
62 	struct spu *spu = ctx->spu;  in spu_hw_mbox_stat_poll()  local
66 	spin_lock_irq(&spu->register_lock);  in spu_hw_mbox_stat_poll()
67 	stat = in_be32(&spu->problem->mb_stat_R);  in spu_hw_mbox_stat_poll()
78 			spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);  in spu_hw_mbox_stat_poll()
79 			spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);  in spu_hw_mbox_stat_poll()
86 			spu_int_stat_clear(spu, 2,  in spu_hw_mbox_stat_poll()
88 			spu_int_mask_or(spu, 2,  in spu_hw_mbox_stat_poll()
92 	spin_unlock_irq(&spu->register_lock);  in spu_hw_mbox_stat_poll()
98 	struct spu *spu = ctx->spu;  in spu_hw_ibox_read()  local
99 	struct spu_problem __iomem *prob = spu->problem;  in spu_hw_ibox_read()
100 	struct spu_priv2 __iomem *priv2 = spu->priv2;  in spu_hw_ibox_read()
103 	spin_lock_irq(&spu->register_lock);  in spu_hw_ibox_read()
110 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);  in spu_hw_ibox_read()
113 	spin_unlock_irq(&spu->register_lock);  in spu_hw_ibox_read()
119 	struct spu *spu = ctx->spu;  in spu_hw_wbox_write()  local
120 	struct spu_problem __iomem *prob = spu->problem;  in spu_hw_wbox_write()
123 	spin_lock_irq(&spu->register_lock);  in spu_hw_wbox_write()
131 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);  in spu_hw_wbox_write()
134 	spin_unlock_irq(&spu->register_lock);  in spu_hw_wbox_write()
140 	out_be32(&ctx->spu->problem->signal_notify1, data);  in spu_hw_signal1_write()
145 	out_be32(&ctx->spu->problem->signal_notify2, data);  in spu_hw_signal2_write()
150 	struct spu *spu = ctx->spu;  in spu_hw_signal1_type_set()  local
151 	struct spu_priv2 __iomem *priv2 = spu->priv2;  in spu_hw_signal1_type_set()
154 	spin_lock_irq(&spu->register_lock);  in spu_hw_signal1_type_set()
161 	spin_unlock_irq(&spu->register_lock);  in spu_hw_signal1_type_set()
166 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);  in spu_hw_signal1_type_get()
171 	struct spu *spu = ctx->spu;  in spu_hw_signal2_type_set()  local
172 	struct spu_priv2 __iomem *priv2 = spu->priv2;  in spu_hw_signal2_type_set()
175 	spin_lock_irq(&spu->register_lock);  in spu_hw_signal2_type_set()
182 	spin_unlock_irq(&spu->register_lock);  in spu_hw_signal2_type_set()
187 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);  in spu_hw_signal2_type_get()
192 	return in_be32(&ctx->spu->problem->spu_npc_RW);  in spu_hw_npc_read()
197 	out_be32(&ctx->spu->problem->spu_npc_RW, val);  in spu_hw_npc_write()
202 	return in_be32(&ctx->spu->problem->spu_status_R);  in spu_hw_status_read()
207 	return ctx->spu->local_store;  in spu_hw_get_ls()
212 	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);  in spu_hw_privcntl_write()
217 	return in_be32(&ctx->spu->problem->spu_runcntl_RW);  in spu_hw_runcntl_read()
222 	spin_lock_irq(&ctx->spu->register_lock);  in spu_hw_runcntl_write()
226 	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);  in spu_hw_runcntl_write()
227 	spin_unlock_irq(&ctx->spu->register_lock);  in spu_hw_runcntl_write()
232 	spin_lock_irq(&ctx->spu->register_lock);  in spu_hw_runcntl_stop()
233 	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);  in spu_hw_runcntl_stop()
234 	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)  in spu_hw_runcntl_stop()
236 	spin_unlock_irq(&ctx->spu->register_lock);  in spu_hw_runcntl_stop()
241 	struct spu *spu = ctx->spu;  in spu_hw_master_start()  local
244 	spin_lock_irq(&spu->register_lock);  in spu_hw_master_start()
245 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;  in spu_hw_master_start()
246 	spu_mfc_sr1_set(spu, sr1);  in spu_hw_master_start()
247 	spin_unlock_irq(&spu->register_lock);  in spu_hw_master_start()
252 	struct spu *spu = ctx->spu;  in spu_hw_master_stop()  local
255 	spin_lock_irq(&spu->register_lock);  in spu_hw_master_stop()
256 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;  in spu_hw_master_stop()
257 	spu_mfc_sr1_set(spu, sr1);  in spu_hw_master_stop()
258 	spin_unlock_irq(&spu->register_lock);  in spu_hw_master_stop()
263 	struct spu_problem __iomem *prob = ctx->spu->problem;  in spu_hw_set_mfc_query()
266 	spin_lock_irq(&ctx->spu->register_lock);  in spu_hw_set_mfc_query()
274 	spin_unlock_irq(&ctx->spu->register_lock);  in spu_hw_set_mfc_query()
280 	return in_be32(&ctx->spu->problem->dma_tagstatus_R);  in spu_hw_read_mfc_tagstatus()
285 	return in_be32(&ctx->spu->problem->dma_qstatus_R);  in spu_hw_get_mfc_free_elements()
292 	struct spu_problem __iomem *prob = ctx->spu->problem;  in spu_hw_send_mfc_command()
294 	spin_lock_irq(&ctx->spu->register_lock);  in spu_hw_send_mfc_command()
302 	spin_unlock_irq(&ctx->spu->register_lock);  in spu_hw_send_mfc_command()
316 	struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;  in spu_hw_restart_dma()
318 	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))  in spu_hw_restart_dma()