294 	unsigned long stat, mask;  in spu_irq_class_0()  local
300 	stat = spu_int_stat_get(spu, 0) & mask;  in spu_irq_class_0()
302 	spu->class_0_pending |= stat;  in spu_irq_class_0()
308 	spu_int_stat_clear(spu, 0, stat);  in spu_irq_class_0()
318 	unsigned long stat, mask, dar, dsisr;  in spu_irq_class_1()  local
325 	stat  = spu_int_stat_get(spu, 1) & mask;  in spu_irq_class_1()
328 	if (stat & CLASS1_STORAGE_FAULT_INTR)  in spu_irq_class_1()
330 	spu_int_stat_clear(spu, 1, stat);  in spu_irq_class_1()
332 	pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,  in spu_irq_class_1()
335 	if (stat & CLASS1_SEGMENT_FAULT_INTR)  in spu_irq_class_1()
338 	if (stat & CLASS1_STORAGE_FAULT_INTR)  in spu_irq_class_1()
341 	if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR)  in spu_irq_class_1()
344 	if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)  in spu_irq_class_1()
352 	return stat ? IRQ_HANDLED : IRQ_NONE;  in spu_irq_class_1()
359 	unsigned long stat;  in spu_irq_class_2()  local
366 	stat = spu_int_stat_get(spu, 2);  in spu_irq_class_2()
369 	stat &= mask;  in spu_irq_class_2()
372 	if (stat & mailbox_intrs)  in spu_irq_class_2()
373 		spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));  in spu_irq_class_2()
375 	spu_int_stat_clear(spu, 2, stat);  in spu_irq_class_2()
377 	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);  in spu_irq_class_2()
379 	if (stat & CLASS2_MAILBOX_INTR)  in spu_irq_class_2()
382 	if (stat & CLASS2_SPU_STOP_INTR)  in spu_irq_class_2()
385 	if (stat & CLASS2_SPU_HALT_INTR)  in spu_irq_class_2()
388 	if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)  in spu_irq_class_2()
391 	if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)  in spu_irq_class_2()
398 	return stat ? IRQ_HANDLED : IRQ_NONE;  in spu_irq_class_2()
677 static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);