133 static struct mpc52xx_intr __iomem *intr;  variable
161 	io_be_clrbit(&intr->ctrl, 11 - l2irq);  in mpc52xx_extirq_mask()
167 	io_be_setbit(&intr->ctrl, 11 - l2irq);  in mpc52xx_extirq_unmask()
173 	io_be_setbit(&intr->ctrl, 27-l2irq);  in mpc52xx_extirq_ack()
194 	ctrl_reg = in_be32(&intr->ctrl);  in mpc52xx_extirq_set_type()
197 	out_be32(&intr->ctrl, ctrl_reg);  in mpc52xx_extirq_set_type()
223 	io_be_setbit(&intr->main_mask, 16 - l2irq);  in mpc52xx_main_mask()
229 	io_be_clrbit(&intr->main_mask, 16 - l2irq);  in mpc52xx_main_unmask()
246 	io_be_setbit(&intr->per_mask, 31 - l2irq);  in mpc52xx_periph_mask()
252 	io_be_clrbit(&intr->per_mask, 31 - l2irq);  in mpc52xx_periph_unmask()
356 		reg = in_be32(&intr->ctrl);  in mpc52xx_irqhost_map()
410 	intr = of_iomap(picnode, 0);  in mpc52xx_init_irq()
411 	if (!intr)  in mpc52xx_init_irq()
422 	pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);  in mpc52xx_init_irq()
427 	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */  in mpc52xx_init_irq()
428 	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */  in mpc52xx_init_irq()
429 	intr_ctrl = in_be32(&intr->ctrl);  in mpc52xx_init_irq()
435 	out_be32(&intr->ctrl, intr_ctrl);  in mpc52xx_init_irq()
438 	out_be32(&intr->per_pri1, 0);  in mpc52xx_init_irq()
439 	out_be32(&intr->per_pri2, 0);  in mpc52xx_init_irq()
440 	out_be32(&intr->per_pri3, 0);  in mpc52xx_init_irq()
441 	out_be32(&intr->main_pri1, 0);  in mpc52xx_init_irq()
442 	out_be32(&intr->main_pri2, 0);  in mpc52xx_init_irq()
492 	status = in_be32(&intr->enc_status);  in mpc52xx_get_irq()