Lines Matching refs:C
697 #define C(x) PERF_COUNT_HW_CACHE_##x macro
704 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
705 [ C(L1D) ] = {
706 [ C(OP_READ) ] = {
707 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
708 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
710 [ C(OP_WRITE) ] = {
711 [ C(RESULT_ACCESS) ] = 0,
712 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
714 [ C(OP_PREFETCH) ] = {
715 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
716 [ C(RESULT_MISS) ] = 0,
719 [ C(L1I) ] = {
720 [ C(OP_READ) ] = {
721 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
722 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
724 [ C(OP_WRITE) ] = {
725 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
726 [ C(RESULT_MISS) ] = -1,
728 [ C(OP_PREFETCH) ] = {
729 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
730 [ C(RESULT_MISS) ] = 0,
733 [ C(LL) ] = {
734 [ C(OP_READ) ] = {
735 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
736 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
738 [ C(OP_WRITE) ] = {
739 [ C(RESULT_ACCESS) ] = PM_L2_ST,
740 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
742 [ C(OP_PREFETCH) ] = {
743 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
744 [ C(RESULT_MISS) ] = 0,
747 [ C(DTLB) ] = {
748 [ C(OP_READ) ] = {
749 [ C(RESULT_ACCESS) ] = 0,
750 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
752 [ C(OP_WRITE) ] = {
753 [ C(RESULT_ACCESS) ] = -1,
754 [ C(RESULT_MISS) ] = -1,
756 [ C(OP_PREFETCH) ] = {
757 [ C(RESULT_ACCESS) ] = -1,
758 [ C(RESULT_MISS) ] = -1,
761 [ C(ITLB) ] = {
762 [ C(OP_READ) ] = {
763 [ C(RESULT_ACCESS) ] = 0,
764 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
766 [ C(OP_WRITE) ] = {
767 [ C(RESULT_ACCESS) ] = -1,
768 [ C(RESULT_MISS) ] = -1,
770 [ C(OP_PREFETCH) ] = {
771 [ C(RESULT_ACCESS) ] = -1,
772 [ C(RESULT_MISS) ] = -1,
775 [ C(BPU) ] = {
776 [ C(OP_READ) ] = {
777 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
778 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
780 [ C(OP_WRITE) ] = {
781 [ C(RESULT_ACCESS) ] = -1,
782 [ C(RESULT_MISS) ] = -1,
784 [ C(OP_PREFETCH) ] = {
785 [ C(RESULT_ACCESS) ] = -1,
786 [ C(RESULT_MISS) ] = -1,
789 [ C(NODE) ] = {
790 [ C(OP_READ) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
794 [ C(OP_WRITE) ] = {
795 [ C(RESULT_ACCESS) ] = -1,
796 [ C(RESULT_MISS) ] = -1,
798 [ C(OP_PREFETCH) ] = {
799 [ C(RESULT_ACCESS) ] = -1,
800 [ C(RESULT_MISS) ] = -1,
805 #undef C