Lines Matching refs:thread
203 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
205 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
207 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
680 &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last; in do_spe_mathemu()
683 current->thread.spefscr_last = __FPU_FPSCR; in do_spe_mathemu()
685 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
695 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) { in do_spe_mathemu()
697 && (current->thread.fpexc_mode & PR_FP_EXC_DIV)) in do_spe_mathemu()
700 && (current->thread.fpexc_mode & PR_FP_EXC_OVF)) in do_spe_mathemu()
703 && (current->thread.fpexc_mode & PR_FP_EXC_UND)) in do_spe_mathemu()
706 && (current->thread.fpexc_mode & PR_FP_EXC_RES)) in do_spe_mathemu()
709 && (current->thread.fpexc_mode & PR_FP_EXC_INV)) in do_spe_mathemu()
756 s_hi = current->thread.evr[fc] & SIGN_BIT_S; in speround_handler()
757 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
802 s_hi = current->thread.evr[fb] & SIGN_BIT_S; in speround_handler()
811 s_hi = current->thread.evr[fb] & SIGN_BIT_S; in speround_handler()
883 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
888 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) in speround_handler()
889 return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0; in speround_handler()