Lines Matching refs:r4
89 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
100 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
109 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
117 neg r6,r4
122 err1; lbz r0,0(r4)
123 addi r4,r4,1
128 err1; lhz r0,0(r4)
129 addi r4,r4,2
134 err1; lwz r0,0(r4)
135 addi r4,r4,4
162 err2; ld r0,0(r4)
163 err2; ld r6,8(r4)
164 err2; ld r7,16(r4)
165 err2; ld r8,24(r4)
166 err2; ld r9,32(r4)
167 err2; ld r10,40(r4)
168 err2; ld r11,48(r4)
169 err2; ld r12,56(r4)
170 err2; ld r14,64(r4)
171 err2; ld r15,72(r4)
172 err2; ld r16,80(r4)
173 err2; ld r17,88(r4)
174 err2; ld r18,96(r4)
175 err2; ld r19,104(r4)
176 err2; ld r20,112(r4)
177 err2; ld r21,120(r4)
178 addi r4,r4,128
216 err1; ld r0,0(r4)
217 err1; ld r6,8(r4)
218 err1; ld r7,16(r4)
219 err1; ld r8,24(r4)
220 err1; ld r9,32(r4)
221 err1; ld r10,40(r4)
222 err1; ld r11,48(r4)
223 err1; ld r12,56(r4)
224 addi r4,r4,64
237 err1; ld r0,0(r4)
238 err1; ld r6,8(r4)
239 err1; ld r7,16(r4)
240 err1; ld r8,24(r4)
241 addi r4,r4,32
250 err1; ld r0,0(r4)
251 err1; ld r6,8(r4)
252 addi r4,r4,16
263 err1; lwz r0,0(r4) /* Less chance of a reject with word ops */
264 err1; lwz r6,4(r4)
265 addi r4,r4,8
271 err1; lwz r0,0(r4)
272 addi r4,r4,4
277 err1; lhz r0,0(r4)
278 addi r4,r4,2
283 err1; lbz r0,0(r4)
302 ld r4,STK_REG(R30)(r1)
311 clrrdi r6,r4,7
345 xor r6,r4,r3
355 err3; lbz r0,0(r4)
356 addi r4,r4,1
361 err3; lhz r0,0(r4)
362 addi r4,r4,2
367 err3; lwz r0,0(r4)
368 addi r4,r4,4
373 err3; ld r0,0(r4)
374 addi r4,r4,8
391 err3; lvx v1,r0,r4
392 addi r4,r4,16
397 err3; lvx v1,r0,r4
398 err3; lvx v0,r4,r9
399 addi r4,r4,32
405 err3; lvx v3,r0,r4
406 err3; lvx v2,r4,r9
407 err3; lvx v1,r4,r10
408 err3; lvx v0,r4,r11
409 addi r4,r4,64
436 err4; lvx v7,r0,r4
437 err4; lvx v6,r4,r9
438 err4; lvx v5,r4,r10
439 err4; lvx v4,r4,r11
440 err4; lvx v3,r4,r12
441 err4; lvx v2,r4,r14
442 err4; lvx v1,r4,r15
443 err4; lvx v0,r4,r16
444 addi r4,r4,128
466 err3; lvx v3,r0,r4
467 err3; lvx v2,r4,r9
468 err3; lvx v1,r4,r10
469 err3; lvx v0,r4,r11
470 addi r4,r4,64
478 err3; lvx v1,r0,r4
479 err3; lvx v0,r4,r9
480 addi r4,r4,32
486 err3; lvx v1,r0,r4
487 addi r4,r4,16
495 err3; ld r0,0(r4)
496 addi r4,r4,8
501 err3; lwz r0,0(r4)
502 addi r4,r4,4
507 err3; lhz r0,0(r4)
508 addi r4,r4,2
513 err3; lbz r0,0(r4)
526 err3; lbz r0,0(r4)
527 addi r4,r4,1
532 err3; lhz r0,0(r4)
533 addi r4,r4,2
538 err3; lwz r0,0(r4)
539 addi r4,r4,4
544 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
545 err3; lwz r7,4(r4)
546 addi r4,r4,8
563 LVS(v16,0,r4) /* Setup permute control vector */
564 err3; lvx v0,0,r4
565 addi r4,r4,16
568 err3; lvx v1,r0,r4
570 addi r4,r4,16
576 err3; lvx v1,r0,r4
578 err3; lvx v0,r4,r9
580 addi r4,r4,32
586 err3; lvx v3,r0,r4
588 err3; lvx v2,r4,r9
590 err3; lvx v1,r4,r10
592 err3; lvx v0,r4,r11
594 addi r4,r4,64
621 err4; lvx v7,r0,r4
623 err4; lvx v6,r4,r9
625 err4; lvx v5,r4,r10
627 err4; lvx v4,r4,r11
629 err4; lvx v3,r4,r12
631 err4; lvx v2,r4,r14
633 err4; lvx v1,r4,r15
635 err4; lvx v0,r4,r16
637 addi r4,r4,128
659 err3; lvx v3,r0,r4
661 err3; lvx v2,r4,r9
663 err3; lvx v1,r4,r10
665 err3; lvx v0,r4,r11
667 addi r4,r4,64
675 err3; lvx v1,r0,r4
677 err3; lvx v0,r4,r9
679 addi r4,r4,32
685 err3; lvx v1,r0,r4
687 addi r4,r4,16
693 addi r4,r4,-16 /* Unwind the +16 load offset */
696 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
697 err3; lwz r6,4(r4)
698 addi r4,r4,8
704 err3; lwz r0,0(r4)
705 addi r4,r4,4
710 err3; lhz r0,0(r4)
711 addi r4,r4,2
716 err3; lbz r0,0(r4)