Lines Matching refs:src
222 struct irq_source src[MAX_IRQ]; member
304 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); in IRQ_check()
306 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { in IRQ_check()
308 priority = IVPR_PRIORITY(opp->src[irq].ivpr); in IRQ_check()
328 struct irq_source *src; in IRQ_local_pipe() local
332 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
337 if (src->output != ILR_INTTGT_INT) { in IRQ_local_pipe()
339 __func__, src->output, n_IRQ, active, was_active, in IRQ_local_pipe()
340 dst->outputs_active[src->output]); in IRQ_local_pipe()
348 dst->outputs_active[src->output]++ == 0) { in IRQ_local_pipe()
350 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
351 mpic_irq_raise(opp, dst, src->output); in IRQ_local_pipe()
355 --dst->outputs_active[src->output] == 0) { in IRQ_local_pipe()
357 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
358 mpic_irq_lower(opp, dst, src->output); in IRQ_local_pipe()
365 priority = IVPR_PRIORITY(src->ivpr); in IRQ_local_pipe()
414 struct irq_source *src; in openpic_update_irq() local
418 src = &opp->src[n_IRQ]; in openpic_update_irq()
419 active = src->pending; in openpic_update_irq()
421 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { in openpic_update_irq()
427 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); in openpic_update_irq()
439 src->ivpr |= IVPR_ACTIVITY_MASK; in openpic_update_irq()
441 src->ivpr &= ~IVPR_ACTIVITY_MASK; in openpic_update_irq()
443 if (src->destmask == 0) { in openpic_update_irq()
449 if (src->destmask == (1 << src->last_cpu)) { in openpic_update_irq()
451 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); in openpic_update_irq()
452 } else if (!(src->ivpr & IVPR_MODE_MASK)) { in openpic_update_irq()
455 if (src->destmask & (1 << i)) { in openpic_update_irq()
462 for (i = src->last_cpu + 1; i != src->last_cpu; i++) { in openpic_update_irq()
466 if (src->destmask & (1 << i)) { in openpic_update_irq()
469 src->last_cpu = i; in openpic_update_irq()
479 struct irq_source *src; in openpic_set_irq() local
486 src = &opp->src[n_IRQ]; in openpic_set_irq()
488 n_IRQ, level, src->ivpr); in openpic_set_irq()
489 if (src->level) { in openpic_set_irq()
491 src->pending = level; in openpic_set_irq()
496 src->pending = 1; in openpic_set_irq()
500 if (src->output != ILR_INTTGT_INT) { in openpic_set_irq()
507 src->pending = 0; in openpic_set_irq()
527 opp->src[i].ivpr = opp->ivpr_reset; in openpic_reset()
529 switch (opp->src[i].type) { in openpic_reset()
531 opp->src[i].level = in openpic_reset()
536 opp->src[i].ivpr |= IVPR_POLARITY_MASK; in openpic_reset()
564 return opp->src[n_IRQ].idr; in read_IRQreg_idr()
570 return opp->src[n_IRQ].output; in read_IRQreg_ilr()
577 return opp->src[n_IRQ].ivpr; in read_IRQreg_ivpr()
583 struct irq_source *src = &opp->src[n_IRQ]; in write_IRQreg_idr() local
595 src->idr = val & mask; in write_IRQreg_idr()
596 pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); in write_IRQreg_idr()
599 if (src->idr & crit_mask) { in write_IRQreg_idr()
600 if (src->idr & normal_mask) { in write_IRQreg_idr()
605 src->output = ILR_INTTGT_CINT; in write_IRQreg_idr()
606 src->nomask = true; in write_IRQreg_idr()
607 src->destmask = 0; in write_IRQreg_idr()
612 if (src->idr & (1UL << n_ci)) in write_IRQreg_idr()
613 src->destmask |= 1UL << i; in write_IRQreg_idr()
616 src->output = ILR_INTTGT_INT; in write_IRQreg_idr()
617 src->nomask = false; in write_IRQreg_idr()
618 src->destmask = src->idr & normal_mask; in write_IRQreg_idr()
621 src->destmask = src->idr; in write_IRQreg_idr()
629 struct irq_source *src = &opp->src[n_IRQ]; in write_IRQreg_ilr() local
631 src->output = val & ILR_INTTGT_MASK; in write_IRQreg_ilr()
632 pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, in write_IRQreg_ilr()
633 src->output); in write_IRQreg_ilr()
651 opp->src[n_IRQ].ivpr = in write_IRQreg_ivpr()
652 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); in write_IRQreg_ivpr()
658 switch (opp->src[n_IRQ].type) { in write_IRQreg_ivpr()
660 opp->src[n_IRQ].level = in write_IRQreg_ivpr()
661 !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); in write_IRQreg_ivpr()
665 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; in write_IRQreg_ivpr()
669 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); in write_IRQreg_ivpr()
675 opp->src[n_IRQ].ivpr); in write_IRQreg_ivpr()
1028 struct irq_source *src; in openpic_cpu_write_internal() local
1050 opp->src[opp->irq_ipi0 + idx].destmask |= val; in openpic_cpu_write_internal()
1097 src = &opp->src[n_IRQ]; in openpic_cpu_write_internal()
1100 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { in openpic_cpu_write_internal()
1130 struct irq_source *src; in openpic_iack() local
1143 src = &opp->src[irq]; in openpic_iack()
1144 if (!(src->ivpr & IVPR_ACTIVITY_MASK) || in openpic_iack()
1145 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { in openpic_iack()
1147 __func__, irq, dst->ctpr, src->ivpr); in openpic_iack()
1153 retval = IVPR_VECTOR(opp, src->ivpr); in openpic_iack()
1156 if (!src->level) { in openpic_iack()
1158 src->ivpr &= ~IVPR_ACTIVITY_MASK; in openpic_iack()
1159 src->pending = 0; in openpic_iack()
1164 src->destmask &= ~(1 << cpu); in openpic_iack()
1165 if (src->destmask && !src->level) { in openpic_iack()
1170 src->ivpr |= IVPR_ACTIVITY_MASK; in openpic_iack()
1325 opp->src[i].level = false; in fsl_common_init()
1329 opp->src[i].type = IRQ_TYPE_FSLINT; in fsl_common_init()
1330 opp->src[i].level = true; in fsl_common_init()
1335 opp->src[i].type = IRQ_TYPE_FSLSPECIAL; in fsl_common_init()
1336 opp->src[i].level = false; in fsl_common_init()
1596 attr32 = opp->src[attr->attr].pending; in mpic_get_attr()