Lines Matching refs:stw
61 stw r3, VCPU_GPR(R3)(r4)
62 stw r5, VCPU_GPR(R5)(r4)
63 stw r6, VCPU_GPR(R6)(r4)
66 stw r3, VCPU_GPR(R4)(r4)
67 stw r5, VCPU_CTR(r4)
70 stw r3, VCPU_PC(r4)
87 stw r3, VCPU_CRIT_SAVE(r4)
151 stw r3, VCPU_CR(r4)
152 stw r7, VCPU_GPR(R7)(r4)
153 stw r8, VCPU_GPR(R8)(r4)
154 stw r9, VCPU_GPR(R9)(r4)
167 stw r8, VCPU_TIMING_EXIT_TBL(r4)
168 stw r9, VCPU_TIMING_EXIT_TBU(r4)
182 stw r9, VCPU_LAST_INST(r4)
184 stw r15, VCPU_GPR(R15)(r4)
185 stw r16, VCPU_GPR(R16)(r4)
186 stw r17, VCPU_GPR(R17)(r4)
187 stw r18, VCPU_GPR(R18)(r4)
188 stw r19, VCPU_GPR(R19)(r4)
189 stw r20, VCPU_GPR(R20)(r4)
190 stw r21, VCPU_GPR(R21)(r4)
191 stw r22, VCPU_GPR(R22)(r4)
192 stw r23, VCPU_GPR(R23)(r4)
193 stw r24, VCPU_GPR(R24)(r4)
194 stw r25, VCPU_GPR(R25)(r4)
195 stw r26, VCPU_GPR(R26)(r4)
196 stw r27, VCPU_GPR(R27)(r4)
197 stw r28, VCPU_GPR(R28)(r4)
198 stw r29, VCPU_GPR(R29)(r4)
199 stw r30, VCPU_GPR(R30)(r4)
200 stw r31, VCPU_GPR(R31)(r4)
208 stw r9, VCPU_FAULT_DEAR(r4)
214 stw r9, VCPU_FAULT_ESR(r4)
218 stw r0, VCPU_GPR(R0)(r4)
219 stw r1, VCPU_GPR(R1)(r4)
220 stw r2, VCPU_GPR(R2)(r4)
221 stw r10, VCPU_GPR(R10)(r4)
222 stw r11, VCPU_GPR(R11)(r4)
223 stw r12, VCPU_GPR(R12)(r4)
224 stw r13, VCPU_GPR(R13)(r4)
225 stw r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
227 stw r3, VCPU_LR(r4)
229 stw r3, VCPU_XER(r4)
295 stw r9, VCPU_SPEFSCR(r4)
302 stw r15, VCPU_GPR(R15)(r4)
303 stw r16, VCPU_GPR(R16)(r4)
304 stw r17, VCPU_GPR(R17)(r4)
305 stw r18, VCPU_GPR(R18)(r4)
306 stw r19, VCPU_GPR(R19)(r4)
307 stw r20, VCPU_GPR(R20)(r4)
308 stw r21, VCPU_GPR(R21)(r4)
309 stw r22, VCPU_GPR(R22)(r4)
310 stw r23, VCPU_GPR(R23)(r4)
311 stw r24, VCPU_GPR(R24)(r4)
312 stw r25, VCPU_GPR(R25)(r4)
313 stw r26, VCPU_GPR(R26)(r4)
314 stw r27, VCPU_GPR(R27)(r4)
315 stw r28, VCPU_GPR(R28)(r4)
316 stw r29, VCPU_GPR(R29)(r4)
317 stw r30, VCPU_GPR(R30)(r4)
318 stw r31, VCPU_GPR(R31)(r4)
356 stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
359 stw r3, HOST_RUN(r1)
361 stw r3, HOST_STACK_LR(r1)
363 stw r5, HOST_CR(r1)
366 stw r14, HOST_NV_GPR(R14)(r1)
367 stw r15, HOST_NV_GPR(R15)(r1)
368 stw r16, HOST_NV_GPR(R16)(r1)
369 stw r17, HOST_NV_GPR(R17)(r1)
370 stw r18, HOST_NV_GPR(R18)(r1)
371 stw r19, HOST_NV_GPR(R19)(r1)
372 stw r20, HOST_NV_GPR(R20)(r1)
373 stw r21, HOST_NV_GPR(R21)(r1)
374 stw r22, HOST_NV_GPR(R22)(r1)
375 stw r23, HOST_NV_GPR(R23)(r1)
376 stw r24, HOST_NV_GPR(R24)(r1)
377 stw r25, HOST_NV_GPR(R25)(r1)
378 stw r26, HOST_NV_GPR(R26)(r1)
379 stw r27, HOST_NV_GPR(R27)(r1)
380 stw r28, HOST_NV_GPR(R28)(r1)
381 stw r29, HOST_NV_GPR(R29)(r1)
382 stw r30, HOST_NV_GPR(R30)(r1)
383 stw r31, HOST_NV_GPR(R31)(r1)
408 stw r3, VCPU_HOST_SPEFSCR(r4)
414 stw r2, HOST_R2(r1)
417 stw r3, VCPU_HOST_PID(r4)
474 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
475 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)