Lines Matching refs:r8
95 lwz r8, HSTATE_PMC5(r13)
101 mtspr SPRN_PMC5, r8
113 ld r8, HSTATE_MMCR2(r13)
115 mtspr SPRN_MMCR2, r8
146 ld r8, 112+PPC_LR_STKOFF(r1)
163 mtsrr0 r8
169 11: mtspr SPRN_HSRR0, r8
175 14: mtspr SPRN_HSRR0, r8
179 15: mtspr SPRN_HSRR0, r8
198 ld r8,VCORE_LPCR(r5)
199 mtspr SPRN_LPCR,r8
577 22: ld r8,VCORE_TB_OFFSET(r5)
578 cmpdi r8,0
581 add r8,r8,r6
582 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
588 addis r8,r8,0x100 /* if so, increment upper 40 bits */
589 mtspr SPRN_TBU40,r8
600 ld r8, VCORE_DPDES(r5)
601 mtspr SPRN_DPDES, r8
618 1: ld r8,VCPU_SLB_E(r6)
620 slbmte r9,r8
642 ld r8,VCPU_SPURR(r4)
644 mtspr SPRN_SPURR,r8
711 ld r8, VCPU_AMR_TM(r4)
716 mtspr SPRN_AMR, r8
782 lwz r8, VCPU_PMC + 16(r4)
788 mtspr SPRN_PMC5, r8
794 ld r8, VCPU_SDAR(r4)
798 mtspr SPRN_SDAR, r8
803 lwz r8, VCPU_PMC + 28(r4)
808 mtspr SPRN_SPMC2, r8
845 mfmsr r8
847 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
848 mtmsrd r8
860 ld r8, VCPU_TAR(r4)
864 mtspr SPRN_TAR, r8
869 ld r8, VCPU_EBBHR(r4)
870 mtspr SPRN_EBBHR, r8
874 ld r8, VCPU_TACR(r4)
878 mtspr SPRN_TACR, r8
882 ld r8, VCPU_WORT(r4)
886 mtspr SPRN_WORT, r8
892 ld r8,VCPU_DEC_EXPIRES(r4)
896 add r8,r8,r6
898 subf r3,r7,r8
905 ld r8, VCPU_SPRG3(r4)
909 mtspr SPRN_SPRG3, r8
951 ld r8,VCORE_LPCR(r5)
952 mtspr SPRN_LPCR,r8
984 andi. r8, r11, MSR_EE
985 mfspr r8, SPRN_LPCR
987 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
988 mtspr SPRN_LPCR, r8
1049 ld r8, VCPU_GPR(R8)(r4)
1134 std r8, VCPU_GPR(R8)(r9)
1182 ld r8, VCPU_GPR(R8)(r9)
1292 1: slbmfee r8,r6
1293 andis. r0,r8,SLB_ESID_V@h
1295 add r8,r8,r6 /* put index in */
1297 std r8,VCPU_SLB_E(r7)
1311 ld r8,VCPU_SPURR(r9)
1315 subf r6,r8,r6
1355 mfspr r8, SPRN_EBBHR
1356 std r8, VCPU_EBBHR(r9)
1360 mfspr r8, SPRN_TACR
1364 std r8, VCPU_TACR(r9)
1368 mfspr r8, SPRN_WORT
1372 std r8, VCPU_WORT(r9)
1398 mfspr r8, SPRN_DSCR
1400 std r8, VCPU_DSCR(r9)
1442 mfmsr r8
1444 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1445 mtmsrd r8
1507 mfspr r8, SPRN_AMR
1512 std r8, VCPU_AMR_TM(r9)
1542 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1543 cmpdi r8, 0
1546 LWZX_BE r3, r8, r4
1548 STWX_BE r3, r8, r4
1588 lbz r7, LPPACA_PMCINUSE(r8)
1595 mfspr r8, SPRN_SDAR
1603 std r8, VCPU_SDAR(r9)
1609 mfspr r8, SPRN_PMC6
1615 stw r8, VCPU_PMC + 20(r9)
1620 mfspr r8, SPRN_MMCRS
1624 std r8, VCPU_MMCR + 32(r9)
1670 li r8,LPID_RSVD /* switch to reserved LPID */
1671 mtspr SPRN_LPID,r8
1682 li r8, 0
1683 mtspr SPRN_DPDES, r8
1687 ld r8,VCORE_TB_OFFSET(r5)
1688 cmpdi r8,0
1691 subf r8,r8,r6
1692 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1698 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1699 mtspr SPRN_TBU40,r8
1710 19: lis r8,0x7fff /* MAX_INT@h */
1711 mtspr SPRN_HDEC,r8
1713 16: ld r8,KVM_HOST_LPCR(r4)
1714 mtspr SPRN_LPCR,r8
1718 ld r8,PACA_SLBSHADOWPTR(r13)
1722 LDX_BE r5, r8, r3
1724 LDX_BE r6, r8, r3
1728 1: addi r8,r8,16
1798 ld r8, VCPU_XER(r9)
1800 mtxer r8
1809 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1820 lwz r8, 0(r10)
1824 stw r8, VCPU_LAST_INST(r9)
2200 lwz r8,VCORE_ENTRY_EXIT(r5)
2201 clrldi r8,r8,56
2207 cmpw r4,r8
2530 li r8, XICS_MFRR
2531 stbcix r3, r6, r8 /* clear the IPI */
2556 stbcix r0, r6, r8 /* set the IPI */
2571 ori r8,r5,MSR_FP
2574 oris r8,r8,MSR_VEC@h
2579 oris r8,r8,MSR_VSX@h
2582 mtmsrd r8
2606 ori r8,r9,MSR_FP
2609 oris r8,r8,MSR_VEC@h
2614 oris r8,r8,MSR_VSX@h
2617 mtmsrd r8
2698 lbz r8, VCORE_IN_GUEST(r5)
2699 cmpwi r8, 0
2701 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2706 subf r7, r8, r7
2711 ld r8, TAS_SEQCOUNT(r5)
2712 cmpdi r8, 0
2713 addi r8, r8, 1
2714 std r8, TAS_SEQCOUNT(r5)
2729 addi r8, r8, 1
2730 std r8, TAS_SEQCOUNT(r5)