Lines Matching refs:r5
83 addi r5,r7,-1
84 andc r6,r3,r5 /* round low to line bdy */
86 add r8,r8,r5 /* ensure we get enough */
99 addi r5,r7,-1
100 andc r6,r3,r5 /* round low to line bdy */
102 add r8,r8,r5
129 addi r5,r7,-1
130 andc r6,r3,r5 /* round low to line bdy */
132 add r8,r8,r5 /* ensure we get enough */
156 addi r5,r7,-1
157 andc r6,r3,r5 /* round low to line bdy */
159 add r8,r8,r5 /* ensure we get enough */
163 mfmsr r5 /* Disable MMU Data Relocation */
164 ori r0,r5,MSR_DR
176 mtmsr r5 /* Re-enable MMU Data Relocation */
184 addi r5,r7,-1
185 andc r6,r3,r5 /* round low to line bdy */
187 add r8,r8,r5 /* ensure we get enough */
225 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
229 add r6,r6,r5
236 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
239 add r3,r3,r5
263 mfspr r5,SPRN_HID4
264 or r5,r5,r3
266 mtspr SPRN_HID4,r5
278 mfspr r5,SPRN_HID4
279 andc r5,r5,r3
281 mtspr SPRN_HID4,r5
303 rldicl r5,r6,32,0
304 ori r5,r5,0x100
305 rldicl r5,r5,32,0
307 mtspr SPRN_HID4,r5
334 rldicl r5,r6,32,0
335 ori r5,r5,0x100
336 rldicl r5,r5,32,0
338 mtspr SPRN_HID4,r5
436 mfmsr r5
437 ori r0,r5,MSR_EE
456 mtmsrd r5,1
472 1: mflr r5
473 addi r5,r5,kexec_flag-1b
477 lwz r4,0(r5)
627 mr r29,r5 /* image (virt) */
652 li r5,0x100
658 mflr r5
701 li r5,0