Lines Matching refs:r3

102 	li	r3,-1
137 	rlwinm	r5,r3,0,0,0		/* r5 contains the new enable bit */
138 	rlwinm	r3,r3,0,11,9		/* Turn off the invalidate bit */
139 	rlwinm	r3,r3,0,1,31		/* Turn off the enable bit */
208 	mtspr	SPRN_L2CR,r3
219 	oris	r3,r3,0x0020
221 	mtspr	SPRN_L2CR,r3
228 10:	mfspr	r3,SPRN_L2CR
229 	andis.	r4,r3,0x0020
235 3:	mfspr	r3,SPRN_L2CR
236 	rlwinm.	r4,r3,0,31,31
239 11:	rlwinm	r3,r3,0,11,9		/* Turn off the L2I bit */
241 	mtspr	SPRN_L2CR,r3
249 	oris	r3,r3,0x8000
250 	mtspr	SPRN_L2CR,r3
255 	mfspr	r3,SPRN_MSSCR0
256 	ori	r3,r3,3
258 	mtspr	SPRN_MSSCR0,r3
279 	li	r3,0
281 	mfspr	r3,SPRN_L2CR
294 	li	r3,-1
314 	rlwinm	r5,r3,0,0,0		/* r5 contains the new enable bit */
315 	rlwinm	r3,r3,0,22,20		/* Turn off the invalidate bit */
316 	rlwinm	r3,r3,0,2,31		/* Turn off the enable & PE bits */
317 	rlwinm	r3,r3,0,5,3		/* Turn off the clken bit */
339 	mtspr	SPRN_L3CR,r3
342 	oris	r3,r3,L3CR_L3RES@h		/* Set reserved bit 5 */
343 	mtspr	SPRN_L3CR,r3
345 	oris	r3,r3,L3CR_L3CLKEN@h		/* Set clken */
346 	mtspr	SPRN_L3CR,r3
355 	ori	r3,r3,0x0400
357 	mtspr	SPRN_L3CR,r3
362 10:	mfspr	r3,SPRN_L3CR
363 	andi.	r4,r3,0x0400
367 	rlwinm	r3,r3,0,5,3		/* Turn off the clken bit */
368 	mtspr	SPRN_L3CR,r3
381 	oris	r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
382 	mtspr	SPRN_L3CR,r3
398 	li	r3,0
400 	mfspr	r3,SPRN_L3CR
423 	li	r3,0x4000	/* 512kB / 32B */
424 	mtctr	r3
425 	lis	r3,KERNELBASE@h
427 	lwz	r0,0(r3)
428 	addi	r3,r3,0x0020	/* Go to start of next cache line */
434 	li	r3,0x4000	/* 512kB / 32B */
435 	mtctr	r3
436 	lis	r3,KERNELBASE@h
438 	dcbf	0,r3
439 	addi	r3,r3,0x0020	/* Go to start of next cache line */
444 	mfspr	r3,SPRN_HID0
445 	rlwinm	r3,r3,0,18,15
446 	mtspr	SPRN_HID0,r3
459 	mfspr	r3,SPRN_HID0
460 	ori	r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
463 	mtspr	SPRN_HID0,r3
464 	xori	r3,r3, HID0_ICFI|HID0_DCI
465 	mtspr	SPRN_HID0,r3