Lines Matching refs:r4
70 mr r31,r4
82 mr r25,r4
104 addis r4,r8,(kernstart_addr - 0b)@ha
105 addi r4,r4,(kernstart_addr - 0b)@l
106 lwz r5,4(r4)
123 lis r4,KERNELBASE@h
124 ori r4,r4,KERNELBASE@l
126 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
128 add r3,r4,r3 /* Required Virtual Address */
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
235 addi r4,r2,THREAD /* init task's THREAD */
236 mtspr SPRN_SPRG_THREAD,r4
251 mr r4,r31
276 mr r4,r31
285 lis r4, KERNELBASE@h
286 ori r4, r4, KERNELBASE@l
287 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
291 lis r4,start_kernel@h
292 ori r4,r4,start_kernel@l
295 mtspr SPRN_SRR0,r4
381 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
867 lwz r4,last_task_used_spe@l(r3)
868 cmpi 0,r4,0
870 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
871 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
875 evstddx evr10, r4, r5 /* save off accumulator */
876 lwz r5,PT_REGS(r4)
877 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
879 andc r4,r4,r10 /* disable SPE for previous task */
880 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
886 li r4,1
888 stw r4,THREAD_USED_SPE(r5)
893 subi r4,r5,THREAD
894 stw r4,last_task_used_spe@l(r3)
909 mr r4,r2 /* current */
941 andc r4,r12,r10 /* r4 = page base */
942 or r4,r4,r11 /* r4 = devtree phys addr */
1027 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1030 li r4,THREAD_ACC
1031 evstddx evr6, r4, r3 /* save off accumulator */
1033 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1035 andc r4,r4,r3 /* disable SPE for previous task */
1036 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1040 lis r4,last_task_used_spe@ha
1041 stw r5,last_task_used_spe@l(r4)
1072 stw r4, 0x4(r5)
1085 li r4,32
1089 slw r5,r4,r5 /* r5 = cache block size */
1103 lis r4,KERNELBASE@h
1106 1: lwz r3,0(r4) /* Load... */
1107 add r4,r4,r5
1111 lis r4,KERNELBASE@h
1114 1: dcbf 0,r4 /* ...and flush. */
1115 add r4,r4,r5
1130 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
1132 rlwimi r4, r5, 0, 3
1136 mtspr SPRN_L1CSR0, r4
1139 1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
1140 andi. r4, r4, 2
1143 mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
1145 rlwimi r4, r5, 0, 3
1147 mtspr SPRN_L1CSR1, r4
1169 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1170 lwz r4,0(r4)
1173 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1184 mr r4,r24 /* Why? */
1198 addi r4,r2,THREAD /* address of our thread_struct */
1199 mtspr SPRN_SPRG_THREAD,r4
1202 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1203 mtspr SPRN_MAS4,r4
1206 lis r4,MSR_KERNEL@h
1207 ori r4,r4,MSR_KERNEL@l
1211 mtspr SPRN_SRR1,r4
1233 mfspr r4,SPRN_PID
1234 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1235 mtspr SPRN_MAS6,r4
1236 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1238 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1239 mtspr SPRN_MAS0,r4
1241 mfspr r4,SPRN_MAS1
1242 andis. r4,r4,MAS1_VALID@h
1247 0: mflr r4
1248 tlbsx 0,r4
1250 mfspr r4,SPRN_MAS1
1251 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1252 mtspr SPRN_MAS1,r4
1254 mfspr r4,SPRN_MAS0
1255 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1256 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1257 mtspr SPRN_MAS0,r4
1262 mfmsr r4
1263 ori r4,r4,MSR_IS | MSR_DS
1265 mtspr SPRN_SRR1,r4
1289 add r9,r9,r4
1290 add r5,r5,r4
1291 add r0,r0,r4
1313 cmpwi r4,0