Lines Matching refs:r3
69 mr r30,r3
77 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
81 mr r23,r3
86 addis r3,r8,(is_second_reloc - 0b)@ha
87 lwz r19,(is_second_reloc - 0b)@l(r3)
102 lis r3,PAGE_OFFSET@h
113 add r3,r3,r5
127 subf r3,r5,r6 /* r3 = r6 - r5 */
128 add r3,r4,r3 /* Required Virtual Address */
250 mr r3,r30
262 lis r3,kernstart_addr@ha
263 la r3,kernstart_addr@l(r3)
265 stw r23,0(r3)
266 stw r25,4(r3)
268 stw r25,0(r3)
275 mr r3,r30
293 lis r3,MSR_KERNEL@h
294 ori r3,r3,MSR_KERNEL@l
296 mtspr SPRN_SRR1,r3
386 addi r3,r1,STACK_FRAME_OVERHEAD
624 1: addi r3,r1,STACK_FRAME_OVERHEAD
866 lis r3,last_task_used_spe@ha
867 lwz r4,last_task_used_spe@l(r3)
894 stw r4,last_task_used_spe@l(r3)
903 lwz r3,_MSR(r1)
904 oris r3,r3,MSR_SPE@h
905 stw r3,_MSR(r1) /* enable use of SPE after return */
907 lis r3,87f@h
908 ori r3,r3,87f@l
932 tlbsx 0,r3 /* must succeed */
940 and r11,r3,r10 /* r11 = page offset */
944 mfspr r3,SPRN_MAS7
955 li r3,DebugDebug@l
956 mtspr SPRN_IVOR15,r3
957 li r3,SPEUnavailable@l
958 mtspr SPRN_IVOR32,r3
959 li r3,SPEFloatingPointData@l
960 mtspr SPRN_IVOR33,r3
961 li r3,SPEFloatingPointRound@l
962 mtspr SPRN_IVOR34,r3
971 li r3,DebugCrit@l
972 mtspr SPRN_IVOR15,r3
973 li r3,SPEUnavailable@l
974 mtspr SPRN_IVOR32,r3
975 li r3,SPEFloatingPointData@l
976 mtspr SPRN_IVOR33,r3
977 li r3,SPEFloatingPointRound@l
978 mtspr SPRN_IVOR34,r3
979 li r3,PerformanceMonitor@l
980 mtspr SPRN_IVOR35,r3
986 li r3,DebugDebug@l
987 mtspr SPRN_IVOR15,r3
988 li r3,PerformanceMonitor@l
989 mtspr SPRN_IVOR35,r3
990 li r3,Doorbell@l
991 mtspr SPRN_IVOR36,r3
992 li r3,CriticalDoorbell@l
993 mtspr SPRN_IVOR37,r3
999 li r3,GuestDoorbell@l
1000 mtspr SPRN_IVOR38,r3
1001 li r3,CriticalGuestDoorbell@l
1002 mtspr SPRN_IVOR39,r3
1003 li r3,Hypercall@l
1004 mtspr SPRN_IVOR40,r3
1005 li r3,Ehvpriv@l
1006 mtspr SPRN_IVOR41,r3
1022 cmpi 0,r3,0
1024 addi r3,r3,THREAD /* want THREAD of task */
1025 lwz r5,PT_REGS(r3)
1027 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1031 evstddx evr6, r4, r3 /* save off accumulator */
1034 lis r3,MSR_SPE@h
1035 andc r4,r4,r3 /* disable SPE for previous task */
1074 mtspr SPRN_PID,r3
1079 mfspr r3,SPRN_L1CFG0
1081 rlwinm r5,r3,9,3 /* Extract cache block size */
1091 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1106 1: lwz r3,0(r4) /* Load... */
1156 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1157 lwz r3,0(r3)
1158 mtctr r3
1162 mr r27,r3 /* tlb entry */
1164 1: mr r3,r26
1168 mr r3,r27 /* tlb entry */
1179 lis r3,__secondary_hold_acknowledge@h
1180 ori r3,r3,__secondary_hold_acknowledge@l
1181 stw r24,0(r3)
1183 li r3,0
1208 lis r3,start_secondary@h
1209 ori r3,r3,start_secondary@l
1210 mtspr SPRN_SRR0,r3
1231 mfspr r3,SPRN_TLB1CFG
1232 andi. r3,r3,0xfff
1237 addi r3,r3,-1
1238 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1256 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1304 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1324 3: mr r3,r5