Lines Matching refs:r10

35 	mtspr	SPRN_SPRG_WSCRATCH0, r10;	/* save one register */	     \
36 	mfspr	r10, SPRN_SPRG_THREAD;					     \
37 	stw	r11, THREAD_NORMSAVE(0)(r10);				     \
38 	stw	r13, THREAD_NORMSAVE(2)(r10);				     \
46 	lwz	r11, THREAD_INFO-THREAD(r10);				     \
54 	lwz	r12, THREAD_NORMSAVE(0)(r10);				     \
56 	lwz	r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */		     \
57 	mflr	r10;							     \
58 	stw	r10,_LINK(r11);						     \
66 	lis	r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
67 	addi	r10, r10, STACK_FRAME_REGS_MARKER@l;			     \
68 	stw	r10, 8(r11);						     \
125 	stw	r10,GPR10(r8);						     \
137 	lwz	r10,GPR10(r8);		/* copy regs from exception stack  */\
139 	stw	r10,GPR10(r11);						     \
140 	lwz	r10,GPR11(r8);						     \
142 	stw	r10,GPR11(r11);						     \
146 	lwz	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11);		     \
148 	stw	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8);		     \
154 	mflr	r10;							     \
155 	stw	r10,_LINK(r11);						     \
186 	mtspr	SPRN_SPRG_WSCRATCH0, r10;	/* save one register */	     \
187 	mfspr	r10, SPRN_SPRG_THREAD;					     \
188 	stw	r11, THREAD_NORMSAVE(0)(r10);				     \
190 	stw	r13, THREAD_NORMSAVE(2)(r10);				     \
227 	li	r10,trap;					\
228 	stw	r10,_TRAP(r11);					\
229 	lis	r10,msr@h;					\
230 	ori	r10,r10,msr@l;					\
231 	copyee(r10, r9);					\
280 	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
281 	andis.	r10,r10,(DBSR_IC|DBSR_BT)@h;				      \
284 	lis	r10,interrupt_base@h;	/* check if exception in vectors */   \
285 	ori	r10,r10,interrupt_base@l;				      \
286 	cmplw	r12,r10;						      \
289 	lis	r10,interrupt_end@h;					      \
290 	ori	r10,r10,interrupt_end@l;				      \
291 	cmplw	r12,r10;						      \
296 	lis	r10,(DBSR_IC|DBSR_BT)@h;	/* clear the IC event */      \
297 	mtspr	SPRN_DBSR,r10;						      \
299 	lwz	r10,_CCR(r11);						      \
302 	mtcrf	0x80,r10;						      \
309 	lwz	r10,GPR10(r8);						      \
333 	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
334 	andis.	r10,r10,(DBSR_IC|DBSR_BT)@h;				      \
337 	lis	r10,interrupt_base@h;	/* check if exception in vectors */   \
338 	ori	r10,r10,interrupt_base@l;				      \
339 	cmplw	r12,r10;						      \
342 	lis	r10,interrupt_end@h;					      \
343 	ori	r10,r10,interrupt_end@l;				      \
344 	cmplw	r12,r10;						      \
349 	lis	r10,(DBSR_IC|DBSR_BT)@h;	/* clear the IC event */      \
350 	mtspr	SPRN_DBSR,r10;						      \
352 	lwz	r10,_CCR(r11);						      \
355 	mtcrf	0x80,r10;						      \
362 	lwz	r10,GPR10(r8);						      \