Lines Matching refs:r8
606 add r10, r10, r8 ;b 151f
748 lis r8, MI_RSV4I@h
749 ori r8, r8, 0x1c00
751 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
756 mr r8, r10
769 lis r8, KERNELBASE@h /* Create vaddr for TLB */
770 ori r8, r8, MI_EVALID /* Mark it valid */
771 mtspr SPRN_MI_EPN, r8
772 mtspr SPRN_MD_EPN, r8
773 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
774 ori r8, r8, MI_SVALID /* Make it valid */
775 mtspr SPRN_MI_TWC, r8
776 li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */
777 ori r8, r8, MI_SVALID /* Make it valid */
778 mtspr SPRN_MD_TWC, r8
779 li r8, MI_BOOTINIT /* Create RPN for address 0 */
780 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
781 mtspr SPRN_MD_RPN, r8
782 lis r8, MI_APG_INIT@h /* Set protection modes */
783 ori r8, r8, MI_APG_INIT@l
784 mtspr SPRN_MI_AP, r8
785 lis r8, MD_APG_INIT@h
786 ori r8, r8, MD_APG_INIT@l
787 mtspr SPRN_MD_AP, r8
799 mr r8, r9 /* Create vaddr for TLB */
800 ori r8, r8, MD_EVALID /* Mark it valid */
801 mtspr SPRN_MD_EPN, r8
802 li r8, MD_PS8MEG /* Set 8M byte page */
803 ori r8, r8, MD_SVALID /* Make it valid */
804 mtspr SPRN_MD_TWC, r8
805 mr r8, r9 /* Create paddr for TLB */
806 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
807 mtspr SPRN_MD_RPN, r8
815 lis r8, KERNELBASE@h /* Create vaddr for TLB */
816 addis r8, r8, 0x0080 /* Add 8M */
817 ori r8, r8, MI_EVALID /* Mark it valid */
818 mtspr SPRN_MD_EPN, r8
829 addis r8, r8, 0x0080 /* Add 8M */
830 mtspr SPRN_MD_EPN, r8
840 lis r8, IDC_INVALL@h
841 mtspr SPRN_IC_CST, r8
842 mtspr SPRN_DC_CST, r8
843 lis r8, IDC_ENABLE@h
844 mtspr SPRN_IC_CST, r8
846 mtspr SPRN_DC_CST, r8
851 lis r8, DC_SFWT@h
852 mtspr SPRN_DC_CST, r8
853 lis r8, IDC_ENABLE@h
854 mtspr SPRN_DC_CST, r8