Lines Matching refs:r10
132 mfcr r10; \
137 mtspr SPRN_SPRG_SCRATCH0,r10; \
154 stw r10,_CCR(r11); /* save registers */ \
157 mfspr r10,SPRN_SPRG_SCRATCH0; \
158 stw r10,GPR10(r11); \
161 mflr r10; \
162 stw r10,_LINK(r11); \
168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
169 MTMSRD(r10); /* (except for mach check in rtas) */ \
178 mfspr r10,SPRN_SPRG_SCRATCH0; \
200 li r10,trap; \
201 stw r10,_TRAP(r11); \
202 li r10,MSR_KERNEL; \
203 copyee(r10, r9); \
336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
337 mfcr r10
343 mtcr r10
344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
357 lwz r10, 0(r10) /* Get the pte */
360 rlwimi r11, r10, 0, 25, 26
365 rlwinm r11, r10, 32-5, _PAGE_PRESENT
366 and r11, r11, r10
367 rlwimi r10, r11, 0, _PAGE_PRESENT
376 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
377 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
392 mfcr r10
403 mtcr r10
404 mfspr r10, SPRN_MD_EPN
407 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
413 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
414 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
415 lwz r10, 0(r10) /* Get the pte */
423 rlwimi r11, r10, 0, 26, 27
427 rlwimi r11, r10, 32-5, 30, 30
440 rlwinm r11, r10, 32-5, _PAGE_PRESENT
441 and r11, r11, r10
442 rlwimi r10, r11, 0, _PAGE_PRESENT
451 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
452 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
453 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
472 andis. r10,r5,0x4000
485 mfcr r10
496 andis. r10,r5,0x4000
499 1: li r10,RPN_PATTERN
500 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
530 mtspr SPRN_SPRG_SCRATCH2, r10
532 mfspr r10, SPRN_SRR0
533 IS_KERNEL(r11, r10)
538 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
542 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
545 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
550 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
551 rlwinm r10, r10, 0, 21, 5
552 cmpwi cr0, r10, 2028 /* Is dcbz? */
554 cmpwi cr0, r10, 940 /* Is dcbi? */
556 cmpwi cr0, r10, 108 /* Is dcbst? */
558 cmpwi cr0, r10, 172 /* Is dcbf? */
560 cmpwi cr0, r10, 1964 /* Is icbi? */
562 141: mfspr r10,SPRN_SPRG_SCRATCH2
565 144: mfspr r10, SPRN_DSISR
566 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
567 mtspr SPRN_DSISR, r10
570 andis. r10,r11,0x1f /* test if reg RA is r0 */
571 li r10,modified_instr@l
572 dcbtst r0,r10 /* touch for store */
576 stw r11,0(r10) /* store add/and instruction */
577 dcbf 0,r10 /* flush new instr. to memory. */
578 icbi 0,r10 /* invalidate instr. cache line */
580 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
585 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
586 143: mtdar r10 /* store faulting EA in DAR */
587 mfspr r10,SPRN_SPRG_SCRATCH2
590 mfctr r10
591 mtdar r10 /* save ctr reg in DAR */
592 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
593 addi r10, r10, 150f@l /* add start of table */
594 mtctr r10 /* load ctr with jump address */
595 xor r10, r10, r10 /* sum starts at zero */
598 add r10, r10, r0 ;b 151f
599 add r10, r10, r1 ;b 151f
600 add r10, r10, r2 ;b 151f
601 add r10, r10, r3 ;b 151f
602 add r10, r10, r4 ;b 151f
603 add r10, r10, r5 ;b 151f
604 add r10, r10, r6 ;b 151f
605 add r10, r10, r7 ;b 151f
606 add r10, r10, r8 ;b 151f
607 add r10, r10, r9 ;b 151f
610 add r10, r10, r12 ;b 151f
611 add r10, r10, r13 ;b 151f
612 add r10, r10, r14 ;b 151f
613 add r10, r10, r15 ;b 151f
614 add r10, r10, r16 ;b 151f
615 add r10, r10, r17 ;b 151f
616 add r10, r10, r18 ;b 151f
617 add r10, r10, r19 ;b 151f
618 add r10, r10, r20 ;b 151f
619 add r10, r10, r21 ;b 151f
620 add r10, r10, r22 ;b 151f
621 add r10, r10, r23 ;b 151f
622 add r10, r10, r24 ;b 151f
623 add r10, r10, r25 ;b 151f
624 add r10, r10, r26 ;b 151f
625 add r10, r10, r27 ;b 151f
626 add r10, r10, r28 ;b 151f
627 add r10, r10, r29 ;b 151f
628 add r10, r10, r30 ;b 151f
629 add r10, r10, r31
640 mtdar r10 /* save fault EA to DAR */
641 mfspr r10,SPRN_SPRG_SCRATCH2
646 add r10, r10, r11 /* add it */
650 add r10, r10, r11 /* add it */
754 lis r10, (MD_RSV4I | MD_RESETVAL)@h
755 ori r10, r10, 0x1c00
756 mr r8, r10
758 lis r10, MD_RESETVAL@h
761 oris r10, r10, MD_WTDEF@h
763 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
793 addi r10, r10, 0x0100
794 mtspr SPRN_MD_CTR, r10
812 addi r10, r10, 0x0100
813 mtspr SPRN_MD_CTR, r10
826 addi r10, r10, 0x0100
827 mtspr SPRN_MD_CTR, r10