Lines Matching refs:r4

86 	lis	r4,KERNELBASE@h
87 	ori	r4,r4,KERNELBASE@l
89 	rlwinm	r5,r4,0,4,31			/* r5 = KERNELBASE % 256M */
91 	add	r3,r4,r3			/* Required Virutal Address */
107 	addi	r4,r2,THREAD	/* init task's THREAD */
108 	mtspr	SPRN_SPRG_THREAD,r4
158 	li	r4, 0		/* higer 32bit */
166 	subfe	r4,r6,r4
172 	stw	r4,0(r3)
187 	lis	r4,KERNELBASE@h
188 	ori	r4,r4,KERNELBASE@l
191 	subf	r4,r5,r4
195 	add	r7,r7,r4
205 	mr	r4,r31
214 	lis	r4, KERNELBASE@h
215 	ori	r4, r4, KERNELBASE@l
216 	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
224 	lis	r4,start_kernel@h
225 	ori	r4,r4,start_kernel@l
228 	mtspr	SPRN_SRR0,r4
795 	stw	r4, 0x4(r5)
859 	mfmsr	r4				/* Get MSR */
860 	andi.	r4,r4,MSR_IS@l			/* TS=1? */
869 	li	r4,0				/* Start at TLB entry 0 */
871 1:	cmpw	r23,r4				/* Is this our entry? */
873 	tlbwe	r3,r4,PPC44x_TLB_PAGEID		/* If not, inval the entry */
874 skpinv:	addi	r4,r4,1				/* Increment */
875 	cmpwi	r4,64				/* Are we done? */
896 	mr	r4,r25
903 	li r4, 0			/* Load the kernel physical address */
921 	clrrwi	r4,r4,10		/* Mask off the real page number */
932 	tlbwe	r4,r0,PPC44x_TLB_XLAT	/* Load the translation fields */
960 	lis	r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
961 	ori	r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
968 	tlbwe	r4,r0,PPC44x_TLB_XLAT
1033 	addi	r4,r2,THREAD	/* init task's THREAD */
1034 	mtspr	SPRN_SPRG3,r4
1050 	mfmsr	r4				/* Get MSR */
1051 	andi.	r4,r4,MSR_IS@l			/* TS=1? */
1079 	addi		r4,0,0
1089 	tlbwe		r4,r3,0
1096 	addis		r4,r4,0x100
1097 	cmpwi		r4,0
1174 	lis	r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1175 	ori	r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1186 	tlbwe	r4,r0,1
1232 	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
1233 	mtspr	SPRN_IVPR,r4