Lines Matching refs:r10
308 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
314 mfspr r10, SPRN_DEAR /* Get faulting address */
320 cmplw r10, r11
362 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
368 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
372 lis r10,tlb_44x_index@ha
377 lwz r13,tlb_44x_index@l(r10)
392 stw r13,tlb_44x_index@l(r10)
395 mfspr r10,SPRN_DEAR
409 mfspr r10, SPRN_SPRG_RSCRATCH0
419 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
425 mfspr r10, SPRN_SRR0 /* Get faulting address */
431 cmplw r10, r11
458 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
464 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
468 lis r10,tlb_44x_index@ha
473 lwz r13,tlb_44x_index@l(r10)
488 stw r13,tlb_44x_index@l(r10)
491 mfspr r10,SPRN_SRR0
505 mfspr r10, SPRN_SPRG_RSCRATCH0
529 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
530 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
533 li r10,0xf85 /* Mask to apply from PTE */
534 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
535 and r11,r12,r10 /* Mask PTE bits to keep */
536 andi. r10,r12,_PAGE_USER /* User page ? */
548 mfspr r10, SPRN_SPRG_RSCRATCH0
555 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
561 mfspr r10,SPRN_DEAR /* Get faulting address */
567 cmplw cr0,r10,r11
599 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
604 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
606 tlbwe r10,r12,0
616 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
642 mfspr r10,SPRN_SPRG_RSCRATCH0
652 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
658 mfspr r10,SPRN_SRR0 /* Get faulting address */
664 cmplw cr0,r10,r11
682 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
687 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
689 tlbwe r10,r12,0
699 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
725 mfspr r10, SPRN_SPRG_RSCRATCH0
744 li r10,0xf85 /* Mask to apply from PTE */
745 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
746 and r11,r12,r10 /* Mask PTE bits to keep */
747 andi. r10,r12,_PAGE_USER /* User page ? */
759 mfspr r10, SPRN_SPRG_RSCRATCH0