Lines Matching refs:r10
108 mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
111 mfcr r10; /* save CR in r10 for now */\
120 stw r10,_CCR(r11); /* save various registers */\
123 mfspr r10,SPRN_SPRG_SCRATCH0; \
124 stw r10,GPR10(r11); \
127 mflr r10; \
128 stw r10,_LINK(r11); \
129 mfspr r10,SPRN_SPRG_SCRATCH2; \
131 stw r10,GPR1(r11); \
133 stw r10,0(r11); \
148 stw r10,crit_r10@l(0); /* save two registers to work with */\
150 mfcr r10; /* save CR in r10 for now */\
162 stw r10,_CCR(r11); /* save various registers */\
165 mflr r10; \
166 stw r10,_LINK(r11); \
216 li r10,trap; \
217 stw r10,_TRAP(r11); \
218 lis r10,msr@h; \
219 ori r10,r10,msr@l; \
220 copyee(r10, r9); \
263 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
285 mfspr r10, SPRN_ESR
286 andis. r10, r10, ESR_DIZ@h
289 mfspr r10, SPRN_DEAR /* Get faulting address */
295 cmplw r10, r11
310 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
315 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
339 tlbsx r9, 0, r10
361 mfspr r10, SPRN_SPRG_SCRATCH0
386 mfspr r10, SPRN_SPRG_SCRATCH0
452 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
469 mfspr r10, SPRN_DEAR /* Get faulting address */
475 cmplw r10, r11
490 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
495 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
507 rlwimi r10, r12, 0, 20, 31
519 rlwimi r10, r9, 0, 20, 31
544 mfspr r10, SPRN_SPRG_SCRATCH0
552 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
569 mfspr r10, SPRN_SRR0 /* Get faulting address */
575 cmplw r10, r11
590 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
595 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
607 rlwimi r10, r12, 0, 20, 31
619 rlwimi r10, r9, 0, 20, 31
644 mfspr r10, SPRN_SPRG_SCRATCH0
692 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
693 andis. r10,r10,DBSR_IC@h
696 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
699 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
700 cmplwi r10,0x2100
705 lis r10,DBSR_IC@h /* clear the IC event */
706 mtspr SPRN_DBSR,r10
708 lwz r10,_CCR(r11)
711 mtcrf 0x80,r10
716 lwz r10,crit_r10@l(0)
800 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
820 mfspr r10, SPRN_SPRG_SCRATCH0