Lines Matching refs:r3
136 cmpw 0,r3,r31
142 1: mr r31,r3 /* save device tree ptr */
191 mr r26,r3
192 addis r4,r3,KERNELBASE@h /* current address of _start */
219 li r3,1 /* MTX only has 1 cpu */
223 stw r3,__secondary_hold_acknowledge@l(0)
227 cmpw 0,r4,r3
230 mr r24,r3 /* cpu # */
309 addi r3,r1,STACK_FRAME_OVERHEAD; \
373 addi r3,r1,STACK_FRAME_OVERHEAD
394 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
408 li r3,0 /* into the hash table */
427 addi r3,r1,STACK_FRAME_OVERHEAD
448 1: addi r3,r1,STACK_FRAME_OVERHEAD
497 mfspr r3,SPRN_IMISS
499 cmplw 0,r1,r3
509 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
513 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
535 tlbli r3
536 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
537 mtcrf 0x80,r3
540 mfspr r3,SPRN_SRR1
541 rlwinm r1,r3,9,6,6 /* Get load/store bit */
545 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
555 mtcrf 0x80,r3 /* Restore CR0 */
571 mfspr r3,SPRN_DMISS
573 cmplw 0,r1,r3
583 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
587 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
614 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
623 tlbld r3
626 mfspr r3,SPRN_SRR1
627 rlwinm r1,r3,9,6,6 /* Get load/store bit */
630 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
639 mtcrf 0x80,r3 /* Restore CR0 */
655 mfspr r3,SPRN_DMISS
657 cmplw 0,r1,r3
667 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
671 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
694 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
703 tlbld r3
752 1: addi r3,r1,STACK_FRAME_OVERHEAD
757 addi r3,r1,STACK_FRAME_OVERHEAD
769 lis r3,PHYSICAL_START@h /* Destination base address */
773 addi r0,r3,4f@l /* jump to the address of 4f */
793 stwx r0,r6,r3
795 dcbst r6,r3 /* write it to memory */
797 icbi r6,r3 /* flush the icache line */
809 mfspr r3, SPRN_PIR
810 stw r3, __secondary_hold_acknowledge@l(0)
811 mr r24, r3 /* cpu # */
838 lis r3,-KERNELBASE@h
842 lis r3,-KERNELBASE@h
856 tophys(r3,r1)
857 stw r0,0(r3)
867 li r3,0
868 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
873 lis r3,start_secondary@h
874 ori r3,r3,start_secondary@l
875 mtspr SPRN_SRR0,r3
914 lis r3,0x2000 /* Ku = 1, VSID = 0 */
916 3: mtsrin r3,r4
917 addi r3,r3,0x111 /* increment VSID */
923 mfpvr r3
924 srwi r3,r3,16
925 cmpwi r3,1
926 lis r3,BATS@ha
927 addi r3,r3,BATS@l
928 tophys(r3,r3)
929 LOAD_BAT(0,r3,r4,r5)
930 LOAD_BAT(1,r3,r4,r5)
931 LOAD_BAT(2,r3,r4,r5)
932 LOAD_BAT(3,r3,r4,r5)
934 LOAD_BAT(4,r3,r4,r5)
935 LOAD_BAT(5,r3,r4,r5)
936 LOAD_BAT(6,r3,r4,r5)
937 LOAD_BAT(7,r3,r4,r5)
954 li r3,0
955 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
966 li r3,0
980 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
981 FIX_SRR1(r3,r5)
983 mtspr SPRN_SRR1,r3
1006 lis r3,start_kernel@h
1007 ori r3,r3,start_kernel@l
1008 mtspr SPRN_SRR0,r3
1019 lwz r3,MMCONTEXTID(r4)
1020 cmpwi cr0,r3,0
1022 mulli r3,r3,897 /* multiply context by skew factor */
1023 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1024 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1040 mtsrin r3,r4
1041 addi r3,r3,0x111 /* next VSID */
1042 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1119 addi r4, r3, __after_mmu_off - _start
1120 mfmsr r3
1121 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1123 andc r3,r3,r0
1125 mtspr SPRN_SRR1,r3
1178 addis r8,r3,disp_BAT@ha