115 struct eeh_ops *eeh_ops = NULL;  variable
178 	eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);  in eeh_dump_dev_log()
182 	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);  in eeh_dump_dev_log()
188 		eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);  in eeh_dump_dev_log()
192 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);  in eeh_dump_dev_log()
200 		eeh_ops->read_config(pdn, cap, 4, &cfg);  in eeh_dump_dev_log()
204 		eeh_ops->read_config(pdn, cap+4, 4, &cfg);  in eeh_dump_dev_log()
216 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);  in eeh_dump_dev_log()
243 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);  in eeh_dump_dev_log()
324 		eeh_ops->configure_bridge(pe);  in eeh_slot_error_detail()
333 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);  in eeh_slot_error_detail()
394 	ret = eeh_ops->get_state(phb_pe, NULL);  in eeh_phb_check_failure()
517 	ret = eeh_ops->get_state(pe, NULL);  in eeh_dev_check_failure()
546 		ret = eeh_ops->get_state(parent_pe, NULL);  in eeh_dev_check_failure()
655 		rc = eeh_ops->get_state(pe, NULL);  in eeh_pci_enable()
670 	rc = eeh_ops->set_option(pe, function);  in eeh_pci_enable()
679 		rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_pci_enable()
731 	if (pdn && eeh_ops->restore_config)  in eeh_restore_dev_state()
732 		eeh_ops->restore_config(pdn);  in eeh_restore_dev_state()
762 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in pcibios_set_pcie_reset_state()
770 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
773 		eeh_ops->reset(pe, EEH_RESET_HOT);  in pcibios_set_pcie_reset_state()
777 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
780 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in pcibios_set_pcie_reset_state()
832 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in eeh_reset_pe_once()
834 		eeh_ops->reset(pe, EEH_RESET_HOT);  in eeh_reset_pe_once()
836 	eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in eeh_reset_pe_once()
863 		state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_reset_pe()
906 		eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);  in eeh_save_bars()
926 int __init eeh_ops_register(struct eeh_ops *ops)  in eeh_ops_register()
934 	if (eeh_ops && eeh_ops != ops) {  in eeh_ops_register()
936 			__func__, eeh_ops->name, ops->name);  in eeh_ops_register()
940 	eeh_ops = ops;  in eeh_ops_register()
960 	if (eeh_ops && !strcmp(eeh_ops->name, name)) {  in eeh_ops_unregister()
961 		eeh_ops = NULL;  in eeh_ops_unregister()
1019 	if (!eeh_ops) {  in eeh_init()
1023 	} else if ((ret = eeh_ops->init()))  in eeh_init()
1034 		traverse_pci_dn(pdn, eeh_ops->probe, NULL);  in eeh_init()
1042 	if (eeh_ops->post_init) {  in eeh_init()
1043 		ret = eeh_ops->post_init();  in eeh_init()
1087 	eeh_ops->probe(pdn, NULL);  in eeh_add_device_early()
1159 		eeh_ops->probe(pdn, NULL);  in eeh_add_device_late()
1307 	ret = eeh_ops->get_state(pe, NULL);  in eeh_pe_change_owner()
1504 		if (!eeh_ops || !eeh_ops->set_option) {  in eeh_pe_set_option()
1537 	if (!eeh_ops || !eeh_ops->get_state)  in eeh_pe_get_state()
1540 	result = eeh_ops->get_state(pe, NULL);  in eeh_pe_get_state()
1607 	if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)  in eeh_pe_reset()
1612 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1626 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in eeh_pe_reset()
1629 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1681 	if (!eeh_ops || !eeh_ops->err_inject)  in eeh_pe_inject_err()
1692 	return eeh_ops->err_inject(pe, type, func, addr, mask);  in eeh_pe_inject_err()
1744 	if (eeh_ops->post_init)  in eeh_enable_dbgfs_set()
1745 		eeh_ops->post_init();  in eeh_enable_dbgfs_set()