Lines Matching refs:uint64_t
42 uint64_t hour_minute_second_millisecond);
43 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
44 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
46 int64_t opal_cec_power_down(uint64_t request);
49 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
50 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
51 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
53 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
54 uint64_t tce_mem_size);
55 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
56 uint64_t tce_mem_size);
57 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
58 uint64_t offset, uint8_t *data);
59 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
60 uint64_t offset, __be16 *data);
61 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
62 uint64_t offset, __be32 *data);
63 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
64 uint64_t offset, uint8_t data);
65 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
66 uint64_t offset, uint16_t data);
67 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
68 uint64_t offset, uint32_t data);
71 int64_t opal_register_exception_handler(uint64_t opal_exception,
72 uint64_t handler_address,
73 uint64_t glue_cache_line);
74 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
78 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
79 uint64_t eeh_action_token);
80 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
81 uint64_t eeh_action_token);
82 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
83 uint32_t func, uint64_t addr, uint64_t mask);
84 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
88 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
90 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
92 uint64_t starting_real_address,
93 uint64_t starting_pci_address,
94 uint64_t size);
95 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
98 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
99 uint64_t ivt_addr, uint64_t ivt_len,
100 uint64_t reject_array_addr,
101 uint64_t peltv_addr);
102 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
105 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
107 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
108 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
110 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
112 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
114 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
115 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
117 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
119 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
122 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
125 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
126 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
127 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
128 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
129 uint16_t tce_levels, uint64_t tce_table_addr,
130 uint64_t tce_table_size, uint64_t tce_page_size);
131 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
132 uint16_t dma_window_number, uint64_t pci_start_addr,
133 uint64_t pci_mem_size);
134 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
136 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
137 uint64_t diag_buffer_len);
138 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
139 uint64_t diag_buffer_len);
140 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
141 uint64_t diag_buffer_len);
142 int64_t opal_pci_fence_phb(uint64_t phb_id);
143 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
144 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mas…
145 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_a…
149 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
151 int64_t opal_pci_poll(uint64_t phb_id);
153 int64_t opal_check_token(uint64_t token);
154 int64_t opal_reinit_cpus(uint64_t flags);
156 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
157 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
164 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
166 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
167 int64_t opal_send_ack_elog(uint64_t log_id);
170 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
172 int64_t opal_update_flash(uint64_t blk_list);
176 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
180 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
181 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
183 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
184 uint64_t length);
185 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
186 uint64_t length);
189 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
191 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
192 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
193 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
194 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
195 uint64_t msg_len);
196 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
197 uint64_t *msg_len);
198 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
203 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
206 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
207 uint64_t size, uint64_t token);
208 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
209 uint64_t size, uint64_t token);
210 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
211 uint64_t token);
233 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
239 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);