Lines Matching refs:phb_id

55 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
57 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
59 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
61 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
63 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
65 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
67 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
74 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
78 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
80 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
82 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
84 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
88 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
90 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
95 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
98 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
102 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
105 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
107 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
108 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
110 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
112 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
114 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
115 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
117 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
119 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
122 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
128 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
131 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
134 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
138 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
140 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
142 int64_t opal_pci_fence_phb(uint64_t phb_id);
143 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
144 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mas…
145 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_a…
149 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
151 int64_t opal_pci_poll(uint64_t phb_id);
193 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);