Lines Matching refs:u32
13 u32 rcwlr; /* Reset Configuration Word Low Register */
14 u32 rcwhr; /* Reset Configuration Word High Register */
15 u32 reserved1;
16 u32 reserved2;
17 u32 rsr; /* Reset Status Register */
18 u32 rmr; /* Reset Mode Register */
19 u32 rpr; /* Reset Protection Register */
20 u32 rcr; /* Reset Control Register */
21 u32 rcer; /* Reset Control Enable Register */
28 u32 spmr; /* System PLL Mode Register */
29 u32 sccr1; /* System Clock Control Register 1 */
30 u32 sccr2; /* System Clock Control Register 2 */
31 u32 scfr1; /* System Clock Frequency Register 1 */
32 u32 scfr2; /* System Clock Frequency Register 2 */
33 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
34 u32 bcr; /* Bread Crumb Register */
35 u32 psc_ccr[12]; /* PSC Clock Control Registers */
36 u32 spccr; /* SPDIF Clock Control Register */
37 u32 cccr; /* CFM Clock Control Register */
38 u32 dccr; /* DIU Clock Control Register */
39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
40 u32 out_ccr[4]; /* OUT CLK Configure Registers */
41 u32 rsv0[2]; /* Reserved */
42 u32 scfr3; /* System Clock Frequency Register 3 */
43 u32 rsv1[3]; /* Reserved */
44 u32 spll_lock_cnt; /* System PLL Lock Counter */
52 u32 cs_cfg[8]; /* CS config */
53 u32 cs_ctrl; /* CS Control Register */
54 u32 cs_status; /* CS Status Register */
55 u32 burst_ctrl; /* CS Burst Control Register */
56 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
57 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
58 u32 alt; /* Address Latch Timing Register */
61 int mpc512x_cs_config(unsigned int cs, u32 val);
67 u32 pkt_size; /* SCLPC Packet Size Register */
68 u32 start_addr; /* SCLPC Start Address Register */
69 u32 ctrl; /* SCLPC Control Register */
70 u32 enable; /* SCLPC Enable Register */
71 u32 reserved1;
72 u32 status; /* SCLPC Status Register */
73 u32 bytes_done; /* SCLPC Bytes Done Register */
74 u32 emb_sc; /* EMB Share Counter Register */
75 u32 emb_pc; /* EMB Pause Control Register */
76 u32 reserved2[7];
77 u32 data_word; /* LPC RX/TX FIFO Data Word Register */
78 u32 fifo_status; /* LPC RX/TX FIFO Status Register */
79 u32 fifo_ctrl; /* LPC RX/TX FIFO Control Register */
80 u32 fifo_alarm; /* LPC RX/TX FIFO Alarm Register */
114 u32 size;