Lines Matching refs:lo
155 u32 lo; member
162 u32 lo; member
199 .lo = MV64x60_CPU2MEM_0_BASE,
203 .lo = MV64x60_CPU2MEM_1_BASE,
207 .lo = MV64x60_CPU2MEM_2_BASE,
211 .lo = MV64x60_CPU2MEM_3_BASE,
218 .lo = MV64x60_ENET2MEM_0_BASE,
222 .lo = MV64x60_ENET2MEM_1_BASE,
226 .lo = MV64x60_ENET2MEM_2_BASE,
230 .lo = MV64x60_ENET2MEM_3_BASE,
237 .lo = MV64x60_MPSC2MEM_0_BASE,
241 .lo = MV64x60_MPSC2MEM_1_BASE,
245 .lo = MV64x60_MPSC2MEM_2_BASE,
249 .lo = MV64x60_MPSC2MEM_3_BASE,
256 .lo = MV64x60_IDMA2MEM_0_BASE,
260 .lo = MV64x60_IDMA2MEM_1_BASE,
264 .lo = MV64x60_IDMA2MEM_2_BASE,
268 .lo = MV64x60_IDMA2MEM_3_BASE,
299 base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo)) in mv64x60_config_ctlr_windows()
306 out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base); in mv64x60_config_ctlr_windows()
308 out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base); in mv64x60_config_ctlr_windows()
310 out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base); in mv64x60_config_ctlr_windows()
338 .lo = 0x10,
344 .lo = 0x90,
354 .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
359 .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
364 .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
369 .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
376 .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
381 .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
386 .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
391 .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
400 .lo = 0x20,
405 .lo = 0xa0,
422 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0); in mv64x60_config_pci_windows()
442 mv64x60_pci2mem[hose].lo, 0); in mv64x60_config_pci_windows()
447 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits); in mv64x60_config_pci_windows()
457 mv64x60_pci2reg[hose].lo, i); in mv64x60_config_pci_windows()
466 .lo = MV64x60_CPU2PCI0_IO_BASE,
472 .lo = MV64x60_CPU2PCI1_IO_BASE,
481 .lo = MV64x60_CPU2PCI0_MEM_0_BASE,
487 .lo = MV64x60_CPU2PCI1_MEM_0_BASE,
501 out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base); in mv64x60_config_cpu2pci_window()