Lines Matching refs:r4
54 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
85 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
86 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
194 l.sw PT_GPR4(r30),r4 ;\
195 l.mfspr r4,r0,SPR_EEAR_BASE ;\
276 l.sw PT_GPR4(r31),r4 ;\
277 l.mfspr r4,r0,SPR_EEAR_BASE ;\
458 CLEAR_GPR(r4)
494 l.ori r4,r0,0x0
574 l.movhi r4,hi(OF_DT_HEADER)
575 l.ori r4,r4,lo(OF_DT_HEADER)
576 l.sfeq r3,r4
594 CLEAR_GPR(r4)
811 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
816 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
826 l.or r6,r6,r4 // r6 <- r4
835 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
837 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
839 tophys(r3,r4) // r3 <- PA
898 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
903 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
913 l.or r6,r6,r4 // r6 <- r4
928 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
930 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
932 tophys(r3,r4) // r3 <- PA
984 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
985 l.slli r4,r4,0x2 // to get address << 2
986 l.add r5,r4,r3 // r4 is pgd_index(daddr)
991 tophys (r4,r5)
992 l.lwz r3,0x0(r4) // get *pmd value
1010 l.lwz r4,0x0(r4) // get **pmd value
1011 l.and r4,r4,r3 // & PAGE_MASK
1015 l.add r3,r3,r4
1020 l.andi r4,r2,0x1
1021 l.sfne r4,r0 // is pte present
1027 l.and r4,r2,r3 // apply the mask
1037 l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1043 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1044 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1045 l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1087 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1088 l.slli r4,r4,0x2 // to get address << 2
1089 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1094 tophys (r4,r5)
1095 l.lwz r3,0x0(r4) // get *pmd value
1116 l.lwz r4,0x0(r4) // get **pmd value
1117 l.and r4,r4,r3 // & PAGE_MASK
1121 l.add r3,r3,r4
1127 l.andi r4,r2,0x1
1128 l.sfne r4,r0 // is pte present
1134 l.and r4,r2,r3 // apply the mask
1156 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1158 l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1164 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1165 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1166 l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1218 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1219 l.sw TRAMP_SLOT_0(r3),r4
1220 l.sw TRAMP_SLOT_1(r3),r4
1221 l.sw TRAMP_SLOT_4(r3),r4
1222 l.sw TRAMP_SLOT_5(r3),r4
1225 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1226 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1227 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1228 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1230 l.srli r5,r4,26 // check opcode for write access
1281 l.slli r6,r4,6 // original offset shifted left 6 - 2
1284 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1293 l.sub r5,r4,r5 // old_jump - new_jump
1343 l.slli r6,r4,6 // original offset shifted left 6 - 2
1346 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1355 l.add r6,r6,r4 // (orig_off + old_jump)
1360 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1361 l.srli r4,r4,16
1362 l.andi r4,r4,0xfc00 // get opcode part
1363 l.slli r4,r4,16
1364 l.or r6,r4,r6 // l.b(n)f new offset
1368 tophys (r4,r2) // may not be needed (due to shifts down_
1369 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1371 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1373 l.slli r4,r4,4 // the amount of info in imediate of jump
1374 l.srli r4,r4,6 // jump instruction with offset
1375 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1429 l.movhi r4,hi(UART_BASE_ADD)
1432 1: l.lbz r5,5(r4)
1438 l.sb 0(r4),r7
1441 1: l.lbz r5,5(r4)
1497 l.movhi r4,hi(UART_BASE_ADD)
1500 1: l.lbz r5,5(r4)
1506 l.sb 0(r4),r7
1509 1: l.lbz r5,5(r4)
1553 l.addi r4,r0,0x7
1554 l.sb 0x2(r3),r4
1556 l.addi r4,r0,0x0
1557 l.sb 0x1(r3),r4
1559 l.addi r4,r0,0x3
1560 l.sb 0x3(r3),r4
1563 l.ori r4,r5,0x80
1564 l.sb 0x3(r3),r4
1565 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1566 l.sb UART_DLM(r3),r4
1567 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1568 l.sb UART_DLL(r3),r4