Lines Matching refs:r3
82 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
83 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
232 l.addi r1,r3,0x0 ;\
236 l.ori r3,r0,lo(_string_unhandled_exception) ;\
237 l.mfspr r3,r0,SPR_NPC ;\
239 l.andi r3,r3,0x1f00 ;\
242 l.ori r3,r0,lo(_string_epc_prefix) ;\
244 l.mfspr r3,r0,SPR_EPCR_BASE ;\
246 l.ori r3,r0,lo(_string_nl) ;\
248 l.addi r3,r1,0x0 ;\
446 l.or r25,r0,r3 /* pointer to fdt */
452 l.ori r3,r0,0x1
453 l.mtspr r0,r3,SPR_SR
457 CLEAR_GPR(r3)
573 l.lwz r3,0(r25) /* load magic from fdt into r3 */
576 l.sfeq r3,r4
583 l.or r3,r0,r25
593 CLEAR_GPR(r3)
816 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
824 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
837 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
839 tophys(r3,r4) // r3 <- PA
841 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
844 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
903 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
911 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
930 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
932 tophys(r3,r4) // r3 <- PA
934 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
937 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
983 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
986 l.add r5,r4,r3 // r4 is pgd_index(daddr)
992 l.lwz r3,0x0(r4) // get *pmd value
993 l.sfne r3,r0
995 l.andi r3,r3,~PAGE_MASK //0x1fff // ~PAGE_MASK
1003 l.addi r3,r0,0xffffe000 // PAGE_MASK
1011 l.and r4,r4,r3 // & PAGE_MASK
1013 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1014 l.slli r3,r3,0x2 // to get address << 2
1015 l.add r3,r3,r4
1016 l.lwz r2,0x0(r3) // this is pte at last
1023 l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1027 l.and r4,r2,r3 // apply the mask
1032 l.ori r3, r0, 0x1
1033 l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
1034 l.addi r6, r3, -1 // r6 = nsets mask
1042 l.addi r3,r0,0xffffe000 // PAGE_MASK
1043 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1086 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
1089 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1095 l.lwz r3,0x0(r4) // get *pmd value
1096 l.sfne r3,r0
1098 l.andi r3,r3,0x1fff // ~PAGE_MASK
1107 l.addi r3,r0,0xffffe000 // PAGE_MASK
1117 l.and r4,r4,r3 // & PAGE_MASK
1119 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1120 l.slli r3,r3,0x2 // to get address << 2
1121 l.add r3,r3,r4
1122 l.lwz r2,0x0(r3) // this is pte at last
1130 l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1134 l.and r4,r2,r3 // apply the mask
1135 l.andi r3,r2,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1137 l.sfeq r3,r0
1143 l.ori r3, r0, 0x1
1144 l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
1145 l.addi r6, r3, -1 // r6 = nsets mask
1163 l.addi r3,r0,0xffffe000 // PAGE_MASK
1164 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1216 tophys (r3,r5) // r3 is trampoline (physical)
1219 l.sw TRAMP_SLOT_0(r3),r4
1220 l.sw TRAMP_SLOT_1(r3),r4
1221 l.sw TRAMP_SLOT_4(r3),r4
1222 l.sw TRAMP_SLOT_5(r3),r4
1226 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1228 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1267 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1269 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1273 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1275 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1287 l.addi r5,r3,0xc // new jump position (physical)
1299 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1318 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1320 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1324 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1326 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1328 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1331 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1349 l.addi r5,r3,0xc // new jump position (physical)
1360 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1365 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1375 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1423 l.lbz r7,0(r3)
1449 l.addi r3,r3,0x1
1470 l.srl r7,r3,r8
1483 l.srl r7,r3,r8
1551 l.movhi r3,hi(UART_BASE_ADD)
1554 l.sb 0x2(r3),r4
1557 l.sb 0x1(r3),r4
1560 l.sb 0x3(r3),r4
1562 l.lbz r5,3(r3)
1564 l.sb 0x3(r3),r4
1566 l.sb UART_DLM(r3),r4
1568 l.sb UART_DLL(r3),r4
1569 l.sb 0x3(r3),r5