Lines Matching refs:l
33 l.movhi rd,hi(-KERNELBASE) ;\
34 l.add rd,rd,rs
37 l.or gpr,r0,r0
40 l.movhi gpr,hi(symbol) ;\
41 l.ori gpr,gpr,lo(symbol)
54 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
76 #define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
77 #define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
79 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
80 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
82 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
83 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
85 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
86 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
88 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
89 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
91 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
92 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
99 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
100 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
102 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
103 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
105 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
106 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
112 #define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
113 #define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
121 l.lwz reg,0(t1)
158 l.mfspr r30,r0,SPR_ESR_BASE ;\
159 l.andi r30,r30,SPR_SR_SM ;\
160 l.sfeqi r30,0 ;\
162 l.bnf 2f /* kernel_mode */ ;\
168 l.lwz r10,0(r30) ;\
170 l.lwz r1,(TI_KSP)(r30) ;\
176 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
179 l.sw PT_GPR12(r30),r12 ;\
180 l.mfspr r12,r0,SPR_EPCR_BASE ;\
181 l.sw PT_PC(r30),r12 ;\
182 l.mfspr r12,r0,SPR_ESR_BASE ;\
183 l.sw PT_SR(r30),r12 ;\
186 l.sw PT_GPR30(r30),r12 ;\
189 l.sw PT_GPR10(r30),r12 ;\
192 l.sw PT_SP(r30),r12 ;\
194 l.sw PT_GPR4(r30),r4 ;\
195 l.mfspr r4,r0,SPR_EEAR_BASE ;\
199 l.ori r30,r0,(EXCEPTION_SR) ;\
200 l.mtspr r0,r30,SPR_ESR_BASE ;\
203 l.mtspr r0,r30,SPR_EPCR_BASE ;\
204 l.rfe
232 l.addi r1,r3,0x0 ;\
233 l.addi r10,r9,0x0 ;\
235 l.jal _emergency_print ;\
236 l.ori r3,r0,lo(_string_unhandled_exception) ;\
237 l.mfspr r3,r0,SPR_NPC ;\
238 l.jal _emergency_print_nr ;\
239 l.andi r3,r3,0x1f00 ;\
241 l.jal _emergency_print ;\
242 l.ori r3,r0,lo(_string_epc_prefix) ;\
243 l.jal _emergency_print_nr ;\
244 l.mfspr r3,r0,SPR_EPCR_BASE ;\
245 l.jal _emergency_print ;\
246 l.ori r3,r0,lo(_string_nl) ;\
248 l.addi r3,r1,0x0 ;\
249 l.addi r9,r10,0x0 ;\
256 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
259 l.sw PT_GPR12(r31),r12 ;\
260 l.mfspr r12,r0,SPR_EPCR_BASE ;\
261 l.sw PT_PC(r31),r12 ;\
262 l.mfspr r12,r0,SPR_ESR_BASE ;\
263 l.sw PT_SR(r31),r12 ;\
266 l.sw PT_GPR31(r31),r12 ;\
269 l.sw PT_GPR10(r31),r12 ;\
272 l.sw PT_SP(r31),r12 ;\
273 l.sw PT_GPR13(r31),r13 ;\
276 l.sw PT_GPR4(r31),r4 ;\
277 l.mfspr r4,r0,SPR_EEAR_BASE ;\
281 l.ori r31,r0,(EXCEPTION_SR) ;\
282 l.mtspr r0,r31,SPR_ESR_BASE ;\
285 l.mtspr r0,r31,SPR_EPCR_BASE ;\
286 l.rfe
297 l.jr r13
298 l.nop
341 l.j boot_dtlb_miss_handler
342 l.nop
346 l.j boot_itlb_miss_handler
347 l.nop
446 l.or r25,r0,r3 /* pointer to fdt */
452 l.ori r3,r0,0x1
453 l.mtspr r0,r3,SPR_SR
492 l.sw TI_KSP(r31), r1
494 l.ori r4,r0,0x0
509 l.sw (0)(r28),r0
510 l.sfltu r28,r30
511 l.bf 1b
512 l.addi r28,r28,4
515 l.jal _ic_enable
516 l.nop
519 l.jal _dc_enable
520 l.nop
528 l.addi r7,r0,128 /* Maximum number of sets */
530 l.mtspr r5,r0,0x0
531 l.mtspr r6,r0,0x0
533 l.addi r5,r5,1
534 l.addi r6,r6,1
535 l.sfeq r7,r0
536 l.bnf 1b
537 l.addi r7,r7,-1
547 l.mfspr r30,r0,SPR_SR
548 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
549 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
550 l.or r30,r30,r28
551 l.mtspr r0,r30,SPR_SR
552 l.nop
553 l.nop
554 l.nop
555 l.nop
556 l.nop
557 l.nop
558 l.nop
559 l.nop
560 l.nop
561 l.nop
562 l.nop
563 l.nop
564 l.nop
565 l.nop
566 l.nop
567 l.nop
570 l.nop 5
573 l.lwz r3,0(r25) /* load magic from fdt into r3 */
574 l.movhi r4,hi(OF_DT_HEADER)
575 l.ori r4,r4,lo(OF_DT_HEADER)
576 l.sfeq r3,r4
577 l.bf _fdt_found
578 l.nop
580 l.or r25,r0,r0
583 l.or r3,r0,r25
585 l.jalr r24
586 l.nop
627 l.jr r30
628 l.nop
639 l.mfspr r24,r0,SPR_UPR
640 l.andi r26,r24,SPR_UPR_ICP
641 l.sfeq r26,r0
642 l.bf 9f
643 l.nop
646 l.mfspr r6,r0,SPR_SR
647 l.addi r5,r0,-1
648 l.xori r5,r5,SPR_SR_ICE
649 l.and r5,r6,r5
650 l.mtspr r0,r5,SPR_SR
657 l.mfspr r24,r0,SPR_ICCFGR
658 l.andi r26,r24,SPR_ICCFGR_CBS
659 l.srli r28,r26,7
660 l.ori r30,r0,16
661 l.sll r14,r30,r28
667 l.andi r26,r24,SPR_ICCFGR_NCS
668 l.srli r28,r26,3
669 l.ori r30,r0,1
670 l.sll r16,r30,r28
673 l.addi r6,r0,0
674 l.sll r5,r14,r28
679 l.mtspr r0,r6,SPR_ICBIR
680 l.sfne r6,r5
681 l.bf 1b
682 l.add r6,r6,r14
686 l.mfspr r6,r0,SPR_SR
687 l.ori r6,r6,SPR_SR_ICE
688 l.mtspr r0,r6,SPR_SR
689 l.nop
690 l.nop
691 l.nop
692 l.nop
693 l.nop
694 l.nop
695 l.nop
696 l.nop
697 l.nop
698 l.nop
700 l.jr r9
701 l.nop
705 l.mfspr r24,r0,SPR_UPR
706 l.andi r26,r24,SPR_UPR_DCP
707 l.sfeq r26,r0
708 l.bf 9f
709 l.nop
712 l.mfspr r6,r0,SPR_SR
713 l.addi r5,r0,-1
714 l.xori r5,r5,SPR_SR_DCE
715 l.and r5,r6,r5
716 l.mtspr r0,r5,SPR_SR
723 l.mfspr r24,r0,SPR_DCCFGR
724 l.andi r26,r24,SPR_DCCFGR_CBS
725 l.srli r28,r26,7
726 l.ori r30,r0,16
727 l.sll r14,r30,r28
733 l.andi r26,r24,SPR_DCCFGR_NCS
734 l.srli r28,r26,3
735 l.ori r30,r0,1
736 l.sll r16,r30,r28
739 l.addi r6,r0,0
740 l.sll r5,r14,r28
742 l.mtspr r0,r6,SPR_DCBIR
743 l.sfne r6,r5
744 l.bf 1b
745 l.add r6,r6,r14
748 l.mfspr r6,r0,SPR_SR
749 l.ori r6,r6,SPR_SR_DCE
750 l.mtspr r0,r6,SPR_SR
752 l.jr r9
753 l.nop
794 l.mfspr r6,r0,SPR_ESR_BASE //
795 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
796 l.sfeqi r6,0 // r6 == 0x1 --> SM
797 l.bf exit_with_no_dtranslation //
798 l.nop
811 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
816 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
818 l.mfspr r6, r0, SPR_DMMUCFGR
819 l.andi r6, r6, SPR_DMMUCFGR_NTS
820 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
821 l.ori r5, r0, 0x1
822 l.sll r5, r5, r6 // r5 = number DMMU sets
823 l.addi r6, r5, -1 // r6 = nsets mask
824 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
826 l.or r6,r6,r4 // r6 <- r4
827 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
828 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
829 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
830 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
831 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
835 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
836 l.bf 1f // goto out
837 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
841 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
842 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
843 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
844 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
845 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
853 l.rfe // SR <- ESR, PC <- EPC
859 l.j _dispatch_bus_fault
890 l.mfspr r6,r0,SPR_ESR_BASE //
891 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
892 l.sfeqi r6,0 // r6 == 0x1 --> SM
893 l.bf exit_with_no_itranslation
894 l.nop
898 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
903 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
905 l.mfspr r6, r0, SPR_IMMUCFGR
906 l.andi r6, r6, SPR_IMMUCFGR_NTS
907 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
908 l.ori r5, r0, 0x1
909 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
910 l.addi r6, r5, -1 // r6 = nsets mask
911 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
913 l.or r6,r6,r4 // r6 <- r4
914 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
915 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
916 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
917 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
918 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
928 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
929 l.bf 1f // goto out
930 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
934 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
935 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
936 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
937 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
938 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
946 l.rfe // SR <- ESR, PC <- EPC
951 l.j _dispatch_bus_fault
952 l.nop
979 l.mfspr r2,r0,SPR_EEAR_BASE
984 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
985 l.slli r4,r4,0x2 // to get address << 2
986 l.add r5,r4,r3 // r4 is pgd_index(daddr)
992 l.lwz r3,0x0(r4) // get *pmd value
993 l.sfne r3,r0
994 l.bnf d_pmd_none
995 l.andi r3,r3,~PAGE_MASK //0x1fff // ~PAGE_MASK
1003 l.addi r3,r0,0xffffe000 // PAGE_MASK
1010 l.lwz r4,0x0(r4) // get **pmd value
1011 l.and r4,r4,r3 // & PAGE_MASK
1012 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1013 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1014 l.slli r3,r3,0x2 // to get address << 2
1015 l.add r3,r3,r4
1016 l.lwz r2,0x0(r3) // this is pte at last
1020 l.andi r4,r2,0x1
1021 l.sfne r4,r0 // is pte present
1022 l.bnf d_pte_not_present
1023 l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1027 l.and r4,r2,r3 // apply the mask
1029 l.mfspr r6, r0, SPR_DMMUCFGR
1030 l.andi r6, r6, SPR_DMMUCFGR_NTS
1031 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1032 l.ori r3, r0, 0x1
1033 l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
1034 l.addi r6, r3, -1 // r6 = nsets mask
1035 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1037 l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1041 l.mfspr r2,r0,SPR_EEAR_BASE
1042 l.addi r3,r0,0xffffe000 // PAGE_MASK
1043 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1044 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1045 l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1052 l.rfe
1054 l.nop 1
1060 l.rfe
1080 l.mfspr r2,r0,SPR_EEAR_BASE
1087 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1088 l.slli r4,r4,0x2 // to get address << 2
1089 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1095 l.lwz r3,0x0(r4) // get *pmd value
1096 l.sfne r3,r0
1097 l.bnf i_pmd_none
1098 l.andi r3,r3,0x1fff // ~PAGE_MASK
1107 l.addi r3,r0,0xffffe000 // PAGE_MASK
1116 l.lwz r4,0x0(r4) // get **pmd value
1117 l.and r4,r4,r3 // & PAGE_MASK
1118 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1119 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1120 l.slli r3,r3,0x2 // to get address << 2
1121 l.add r3,r3,r4
1122 l.lwz r2,0x0(r3) // this is pte at last
1127 l.andi r4,r2,0x1
1128 l.sfne r4,r0 // is pte present
1129 l.bnf i_pte_not_present
1130 l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1134 l.and r4,r2,r3 // apply the mask
1135 l.andi r3,r2,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1137 l.sfeq r3,r0
1138 l.bf itlb_tr_fill //_workaround
1140 l.mfspr r6, r0, SPR_IMMUCFGR
1141 l.andi r6, r6, SPR_IMMUCFGR_NTS
1142 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1143 l.ori r3, r0, 0x1
1144 l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
1145 l.addi r6, r3, -1 // r6 = nsets mask
1146 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1156 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1158 l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1162 l.mfspr r2,r0,SPR_EEAR_BASE
1163 l.addi r3,r0,0xffffe000 // PAGE_MASK
1164 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1165 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1166 l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1173 l.rfe
1176 l.nop 1
1182 l.rfe
1219 l.sw TRAMP_SLOT_0(r3),r4
1220 l.sw TRAMP_SLOT_1(r3),r4
1221 l.sw TRAMP_SLOT_4(r3),r4
1222 l.sw TRAMP_SLOT_5(r3),r4
1225 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1226 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1227 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1228 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1230 l.srli r5,r4,26 // check opcode for write access
1231 l.sfeqi r5,0 // l.j
1232 l.bf 0f
1233 l.sfeqi r5,0x11 // l.jr
1234 l.bf 1f
1235 l.sfeqi r5,1 // l.jal
1236 l.bf 2f
1237 l.sfeqi r5,0x12 // l.jalr
1238 l.bf 3f
1239 l.sfeqi r5,3 // l.bnf
1240 l.bf 4f
1241 l.sfeqi r5,4 // l.bf
1242 l.bf 5f
1244 l.nop
1245 l.j 99b // should never happen
1246 l.nop 1
1263 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1266 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1267 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1268 l.srli r5,r6,16
1269 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1272 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1273 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1274 l.andi r5,r6,0xffff
1275 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1281 l.slli r6,r4,6 // original offset shifted left 6 - 2
1284 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1287 l.addi r5,r3,0xc // new jump position (physical)
1288 l.slli r5,r5,4 // new jump position: shifted left 4
1293 l.sub r5,r4,r5 // old_jump - new_jump
1294 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1295 l.srli r5,r5,6 // new offset shifted right 2
1299 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1301 l.j trampoline_out
1302 l.nop
1314 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1317 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1318 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1319 l.srli r5,r6,16
1320 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1323 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1324 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1325 l.andi r5,r6,0xffff
1326 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1328 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1329 l.andi r5,r5,0x3ff // clear out opcode part
1330 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1331 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1336 l.j trampoline_out
1337 l.nop
1343 l.slli r6,r4,6 // original offset shifted left 6 - 2
1346 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1349 l.addi r5,r3,0xc // new jump position (physical)
1350 l.slli r5,r5,4 // new jump position: shifted left 4
1355 l.add r6,r6,r4 // (orig_off + old_jump)
1356 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1357 l.srli r6,r6,6 // new offset shifted right 2
1360 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1361 l.srli r4,r4,16
1362 l.andi r4,r4,0xfc00 // get opcode part
1363 l.slli r4,r4,16
1364 l.or r6,r4,r6 // l.b(n)f new offset
1365 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1369 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1371 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1373 l.slli r4,r4,4 // the amount of info in imediate of jump
1374 l.srli r4,r4,6 // jump instruction with offset
1375 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1382 l.mtspr r0,r5,SPR_EPCR_BASE
1393 l.mfspr r21,r0,SPR_ICCFGR
1394 l.andi r21,r21,SPR_ICCFGR_CBS
1395 l.srli r21,r21,7
1396 l.ori r23,r0,16
1397 l.sll r14,r23,r21
1399 l.mtspr r0,r5,SPR_ICBIR
1400 l.add r5,r5,r14
1401 l.mtspr r0,r5,SPR_ICBIR
1403 l.jr r9
1404 l.nop
1423 l.lbz r7,0(r3)
1424 l.sfeq r7,r0
1425 l.bf 9f
1426 l.nop
1429 l.movhi r4,hi(UART_BASE_ADD)
1431 l.addi r6,r0,0x20
1432 1: l.lbz r5,5(r4)
1433 l.andi r5,r5,0x20
1434 l.sfeq r5,r6
1435 l.bnf 1b
1436 l.nop
1438 l.sb 0(r4),r7
1440 l.addi r6,r0,0x60
1441 1: l.lbz r5,5(r4)
1442 l.andi r5,r5,0x60
1443 l.sfeq r5,r6
1444 l.bnf 1b
1445 l.nop
1448 l.j 2b
1449 l.addi r3,r3,0x1
1456 l.jr r9
1457 l.nop
1466 l.addi r8,r0,32 // shift register
1469 l.addi r8,r8,-0x4
1470 l.srl r7,r3,r8
1471 l.andi r7,r7,0xf
1474 l.sfeqi r8,0x4
1475 l.bf 2f
1476 l.nop
1478 l.sfeq r7,r0
1479 l.bf 1b
1480 l.nop
1483 l.srl r7,r3,r8
1485 l.andi r7,r7,0xf
1486 l.sflts r8,r0
1487 l.bf 9f
1489 l.sfgtui r7,0x9
1490 l.bnf 8f
1491 l.nop
1492 l.addi r7,r7,0x27
1495 l.addi r7,r7,0x30
1497 l.movhi r4,hi(UART_BASE_ADD)
1499 l.addi r6,r0,0x20
1500 1: l.lbz r5,5(r4)
1501 l.andi r5,r5,0x20
1502 l.sfeq r5,r6
1503 l.bnf 1b
1504 l.nop
1506 l.sb 0(r4),r7
1508 l.addi r6,r0,0x60
1509 1: l.lbz r5,5(r4)
1510 l.andi r5,r5,0x60
1511 l.sfeq r5,r6
1512 l.bnf 1b
1513 l.nop
1516 l.j 2b
1517 l.addi r8,r8,-0x4
1525 l.jr r9
1526 l.nop
1551 l.movhi r3,hi(UART_BASE_ADD)
1553 l.addi r4,r0,0x7
1554 l.sb 0x2(r3),r4
1556 l.addi r4,r0,0x0
1557 l.sb 0x1(r3),r4
1559 l.addi r4,r0,0x3
1560 l.sb 0x3(r3),r4
1562 l.lbz r5,3(r3)
1563 l.ori r4,r5,0x80
1564 l.sb 0x3(r3),r4
1565 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1566 l.sb UART_DLM(r3),r4
1567 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1568 l.sb UART_DLL(r3),r4
1569 l.sb 0x3(r3),r5
1571 l.jr r9
1572 l.nop