Lines Matching refs:L1_CACHE_BYTES
19 #define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
21 #define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
24 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
33 (ENTRY) * L1_CACHE_BYTES, u32)
36 __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
38 __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
40 __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
42 __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
47 (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
50 (ENTRY) * L1_CACHE_BYTES, u32)
55 (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
58 (ENTRY) * L1_CACHE_BYTES, u32)