Lines Matching refs:uint64_t
41 uint64_t u64;
43 uint64_t upper:2; /* Normally 2 for XKPHYS */
44 uint64_t reserved_49_61:13; /* Must be zero */
45 uint64_t io:1; /* 1 for IO space access */
46 uint64_t did:5; /* PCIe DID = 3 */
47 uint64_t subdid:3; /* PCIe SubDID = 1 */
48 uint64_t reserved_36_39:4; /* Must be zero */
49 uint64_t es:2; /* Endian swap = 1 */
50 uint64_t port:2; /* PCIe port 0,1 */
51 uint64_t reserved_29_31:3; /* Must be zero */
56 uint64_t ty:1;
58 uint64_t bus:8;
64 uint64_t dev:5;
66 uint64_t func:3;
71 uint64_t reg:12;
74 uint64_t upper:2; /* Normally 2 for XKPHYS */
75 uint64_t reserved_49_61:13; /* Must be zero */
76 uint64_t io:1; /* 1 for IO space access */
77 uint64_t did:5; /* PCIe DID = 3 */
78 uint64_t subdid:3; /* PCIe SubDID = 2 */
79 uint64_t reserved_36_39:4; /* Must be zero */
80 uint64_t es:2; /* Endian swap = 1 */
81 uint64_t port:2; /* PCIe port 0,1 */
82 uint64_t address:32; /* PCIe IO address */
85 uint64_t upper:2; /* Normally 2 for XKPHYS */
86 uint64_t reserved_49_61:13; /* Must be zero */
87 uint64_t io:1; /* 1 for IO space access */
88 uint64_t did:5; /* PCIe DID = 3 */
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
90 uint64_t reserved_36_39:4; /* Must be zero */
91 uint64_t address:36; /* PCIe Mem address */
107 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port) in cvmx_pcie_get_io_base_address()
128 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port) in cvmx_pcie_get_io_size()
141 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port) in cvmx_pcie_get_mem_base_address()
160 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port) in cvmx_pcie_get_mem_size()
230 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, in __cvmx_pcie_build_config_addr()
270 uint64_t address = in cvmx_pcie_config_read8()
292 uint64_t address = in cvmx_pcie_config_read16()
314 uint64_t address = in cvmx_pcie_config_read32()
335 uint64_t address = in cvmx_pcie_config_write8()
354 uint64_t address = in cvmx_pcie_config_write16()
373 uint64_t address = in cvmx_pcie_config_write32()
588 uint64_t start_cycle; in __cvmx_pcie_rc_initialize_link_gen1()
1012 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63); in __cvmx_pcie_rc_initialize_gen1()
1093 uint64_t start_cycle; in __cvmx_pcie_rc_initialize_link_gen2()