Lines Matching refs:__raw_writel
115 __raw_writel(r, ctx->regs + PCI_REG_STATCMD); in config_access()
154 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); in config_access()
174 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); in config_access()
334 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); in alchemy_pci_resume()
335 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_resume()
336 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_resume()
337 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_resume()
338 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_resume()
339 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_resume()
340 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); in alchemy_pci_resume()
341 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); in alchemy_pci_resume()
342 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); in alchemy_pci_resume()
343 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); in alchemy_pci_resume()
344 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); in alchemy_pci_resume()
346 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); in alchemy_pci_resume()
435 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
475 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()